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    Memory device having row decoder
    1.
    发明授权
    Memory device having row decoder 有权
    具有行解码器的存储器件

    公开(公告)号：US06198686B1

    公开(公告)日：2001-03-06

    申请号：US09613583

    申请日：2000-07-10

    申请人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

    发明人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

    IPC分类号： G11C800

    CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087

    摘要： On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of-an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.

    摘要翻译： 一方面，通过缓冲器将行地址提供给行地址寄存器11，并且其输出经由互补信号生成电路15和预解码器16提供给字解码器17A。 另一方面，响应于发出激活命令，控制信号AS1经由延迟电路14提供给行地址寄存器11的时钟输入CK作为选通信号AS2，并且提供AS2以减少 定时裕度，经由延迟电路20A到预解码器16的选通信号输入作为选通信号S2。 S2经由延迟电路20B提供给具有RS触发器2301至2332或锁存电路的字解码器17A的选通信号输入。 每个锁存电路由具有设定输入和复位输入的NOR门组成，另一NOR门具有耦合以接收前NOR门的输出和另一组输入的输入，以接收对于所有者共同的多选择信号 字解码器中的锁存电路。

    Semiconductor integrated circuit
    2.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06317353B1

    公开(公告)日：2001-11-13

    申请号：US09536449

    申请日：2000-03-28

    申请人： Toshimi Ikeda ,  Masato Matsumiya ,  Masato Takita

    发明人： Toshimi Ikeda ,  Masato Matsumiya ,  Masato Takita

    IPC分类号： G11C506

    CPC分类号： G11C5/063 ,  G11C5/14

    摘要： A power supply line is formed over a memory cell array which has arranged a plurality of memory cells using a metal wiring layer M1 which is disposed on the side closest to the memory cell array, of all the metal wiring layers. The power supply lines are formed over the memory cell array using not only an upper metal wiring layer M2 but the metal wiring layer M1 so that the wiring resistance of the power supply lines may decrease and a sufficient amount of current can be supplied to the power supply lines. Consequently, the circuits supplied with an electric current through the power supply lines become capable of high-speed operation. This is particularly effective for the high-speed operation of the circuits arranged around the memory cell array. The power supply line formed using the lower metal wiring layer M1 is connected over the memory cell array to a power supply line which is formed using the metal wiring layer M2 on the upper layer than the metal wiring layer M1. Therefore, the netlike configuration of the power supply lines can be made with higher density compared to conventional ones.

    摘要翻译： 电源线形成在存储单元阵列上，该存储单元阵列使用布置在最靠近存储单元阵列的一侧的金属布线层M1布置了多个存储单元。 电源线不仅使用上金属布线层M2而且金属布线层M1形成在存储单元阵列的上方，使得电源线的布线电阻可能降低，并且能够向电源提供足够的电流量 供应线。 因此，通过电源线提供电流的电路变得能够高速运行。 这对于布置在存储单元阵列周围的电路的高速操作特别有效。 使用下金属布线层M1形成的电源线通过存储单元阵列连接到使用上层的金属布线层M2形成的电源线，而不是金属布线层M1。 因此，与常规电源线相比，可以以更高的密度制造电源线的网状结构。

    Memory device having row decoder
    3.
    发明授权
    Memory device having row decoder 有权
    具有行解码器的存储器件

    公开(公告)号：US6111795A

    公开(公告)日：2000-08-29

    申请号：US342059

    申请日：1999-06-29

    申请人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

    发明人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

    IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/408 ,  G11C7/00

    CPC分类号： G11C8/08 ,  G11C11/4076 ,  G11C11/4087 ,  G11C8/10 ,  G11C8/18

    摘要： On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.

    摘要翻译： 一方面，通过缓冲器将行地址提供给行地址寄存器11，并且其输出经由互补信号生成电路15和预解码器16提供给字解码器17A。 另一方面，响应于激活命令的发出，控制信号AS1经由延迟电路14提供给行地址寄存器11的时钟输入CK作为选通信号AS2，并且提供AS2以减少定时 通过延迟电路20A将预解码器16的选通信号输入作为选通信号S2。 S2经由延迟电路20B提供给具有RS触发器2301至2332或锁存电路的字解码器17A的选通信号输入。 每个锁存电路由具有设定输入和复位输入的NOR门组成，另一NOR门具有耦合以接收前NOR门的输出和另一组输入的输入，以接收对于所有者共同的多选择信号 字解码器中的锁存电路。

    Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type
    6.
    发明授权
    Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type 有权
    半导体存储器件，具有过驱动读出放大器和源极跟随器类型的稳定电源电路

    公开(公告)号：US06262930B1

    公开(公告)日：2001-07-17

    申请号：US09612281

    申请日：2000-07-07

    申请人： Kaoru Mori ,  Masato Matsumiya ,  Ayako Kitamoto ,  Shinichi Yamada ,  Yuki Ishii ,  Hideki Kanou ,  Masato Takita

    发明人： Kaoru Mori ,  Masato Matsumiya ,  Ayako Kitamoto ,  Shinichi Yamada ,  Yuki Ishii ,  Hideki Kanou ,  Masato Takita

    IPC分类号： G11C700

    CPC分类号： G11C7/06

    摘要： To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits 26 through 28 each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH0 in response to a selection control signals SC0 and *SC0, a selection control circuit 22 for generating the signals SC0 and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS0 is inactive and Vjj for a predetermined period in response to activation of BRAS0, and sense amplifier driving circuits 111 through 113 for supplying the ground voltage and VH0 to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii=VG−Vth, where Vth is the threshold voltage of the NMOS transistor 45, a leak circuit is employed. The leak circuit has a NMOS transistor connected between Vii and ground. Wasteful power consumption by the current flowing to the leak circuit is negligibly small, e.g. 1 to 10 &mgr;A, and the variation of the supply voltage Vii reduces effectively.

    摘要翻译： 为了减少电流消耗，为每个存储体提供一个电路，其中包括选择电路26至28，每个选择电路26至28用于响应于选择控制信号SC0和*选择正常电源电压Vii或较高电源电压Vjj作为电源电压VH0， SC0，用于产生信号SC0和* SC0的选择控制电路22，以使得当存储体激活信号BRAS0不活动时选择电路选择Vii，并响应于BRAS0的激活而在预定时间段内选择Vjj，读出放大器驱动电路111通过 113，用于响应于感测放大器控制信号的激活而将接地电压和VH0提供给读出放大器行。 为了稳定具有NMOS晶体管的电源电路的输出电压Vii，其漏电极，栅极和源电极处于VCC，VG和大约Vii = VG-Vth，其中Vth是NMOS晶体管45的阈值电压 ，采用泄漏电路。 泄漏电路具有连接在Vii和地之间的NMOS晶体管。 通过流向泄漏电路的电流浪费的功率消耗可忽略不计，例如， 1〜10μA，电源电压Vii的变化有效降低。

    Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type
    7.
    发明授权
    Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type 有权
    半导体存储器件，具有过驱动读出放大器和源极跟随器类型的稳定电源电路

    公开(公告)号：US6115316A

    公开(公告)日：2000-09-05

    申请号：US342060

    申请日：1999-06-29

    申请人： Kaoru Mori ,  Masato Matsumiya ,  Ayako Kitamoto ,  Shinichi Yamada ,  Yuki Ishii ,  Hideki Kanou ,  Masato Takita

    发明人： Kaoru Mori ,  Masato Matsumiya ,  Ayako Kitamoto ,  Shinichi Yamada ,  Yuki Ishii ,  Hideki Kanou ,  Masato Takita

    IPC分类号： G11C7/06 ,  G11C8/00

    CPC分类号： G11C7/06

    摘要： To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits 26 through 28 each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH0 in response to a selection control signals SC0 and *SC0, a selection control circuit 22 for generating the signals SC0 and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS0 is inactive and Vjj for a predetermined period in response to activation of BRAS0, and sense amplifier driving circuits 111 through 113 for supplying the ground voltage and VH0 to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii=VG-Vth, where Vth is the threshold voltage of the NMOS transistor 45, a leak circuit is employed. The leak circuit has a NMOS transistor connected between Vii and ground. Wasteful power consumption by the current flowing to the leak circuit is negligibly small, e.g. 1 to 10 .mu.A, and the variation of the supply voltage Vii reduces effectively.

    摘要翻译： 为了减少电流消耗，为每个存储体提供一个电路，其中包括选择电路26至28，每个选择电路26至28用于响应于选择控制信号SC0和*选择正常电源电压Vii或较高电源电压Vjj作为电源电压VH0， SC0，用于产生信号SC0和* SC0的选择控制电路22，以使得当存储体激活信号BRAS0不活动时选择电路选择Vii，并响应于BRAS0的激活而在预定时间段内选择Vjj，读出放大器驱动电路111通过 113，用于响应于感测放大器控制信号的激活而将接地电压和VH0提供给读出放大器行。 为了稳定具有NMOS晶体管的电源电路的输出电压Vii，其漏电极，栅极和源电极处于VCC，VG和大约Vii = VG-Vth，其中Vth是NMOS晶体管45的阈值电压 ，采用泄漏电路。 泄漏电路具有连接在Vii和地之间的NMOS晶体管。 通过流向泄漏电路的电流浪费的功率消耗可忽略不计，例如， 1至10μA，并且电源电压Vii的变化有效降低。

    Semiconductor memory device capable of driving non-selected word lines to first and second potentials
    8.
    发明申请
    Semiconductor memory device capable of driving non-selected word lines to first and second potentials 失效
    能够将未选择的字线驱动到第一和第二电位的半导体存储器件

    公开(公告)号：US20060098523A1

    公开(公告)日：2006-05-11

    申请号：US11313963

    申请日：2005-12-22

    申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

    发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

    IPC分类号： G11C8/00

    CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

    摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

    摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

    Semiconductor memory device based on dummy-cell method
    9.
    发明授权
    Semiconductor memory device based on dummy-cell method 失效
    基于虚拟单元法的半导体存储器件

    公开(公告)号：US06868023B2

    公开(公告)日：2005-03-15

    申请号：US10656374

    申请日：2003-09-08

    申请人： Masato Takita ,  Shinichi Yamada ,  Masato Matsumiya

    发明人： Masato Takita ,  Shinichi Yamada ,  Masato Matsumiya

    IPC分类号： G11C11/403 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4099 ,  G11C7/00 ,  G11C7/02

    CPC分类号： G11C7/062 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4099

    摘要： A semiconductor memory device includes a plurality of bit line pairs, each of which includes a first bit line and a second bit line, a plurality of memory cells which are coupled to said first bit line, and store electric charge in capacitors, a dummy cell which is coupled to a second bit line, and is charged with a predetermined potential, a sense amplifier which amplifies a potential difference between the first bit line and the second bit line, and a control circuit which charges said dummy cell with the predetermined potential only for a fixed time period.

    摘要翻译： 半导体存储器件包括多个位线对，每个位线对包括第一位线和第二位线，耦合到所述第一位线的多个存储器单元，并将电荷存储在电容器中;虚拟单元 其被耦合到第二位线，并且被充电为预定电位;放大器，用于放大第一位线和第二位线之间的电位差;以及控制电路，其对所述虚设单元充电仅具有预定电位 固定时间段。

    Semiconductor memory employing direct-type sense amplifiers capable of realizing high-speed access
    10.
    发明授权
    Semiconductor memory employing direct-type sense amplifiers capable of realizing high-speed access 有权
    采用直接式读出放大器的半导体存储器，能够实现高速存取

    公开(公告)号：US6147919A

    公开(公告)日：2000-11-14

    申请号：US274245

    申请日：1999-03-23

    申请人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

    发明人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

    IPC分类号： H01L27/10 ,  G11C7/06 ,  G11C7/12 ,  G11C7/02

    CPC分类号： G11C7/06 ,  G11C7/12

    摘要： A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks. The local drivers apply a selection signal to the second selection lines according to a selection signal from the first selection lines. The write-only column selection lines are controlled by signals that are used to control the sense amplifiers.

    摘要翻译： 半导体存储器具有排列成阵列的存储单元，布置在每个存储单元列中的直接型读出放大器，用于向要被访问的存储单元写入数据和从存储单元读取数据;列选择线，用于选择读取放大器 涉及要访问的存储器单元的列，只读列选择线，用于选择存储单元被访问以涉及要访问的存储器单元的行的读出放大器以写入数据，以及本地驱动器。 读出放大器在每行中分组成读出放大器模块。 只写列选择线由用于选择读入放大器块的第一选择线组成，所述读出放大器块包括要被存取的存储单元以进行数据写入，第二选择线用于选择包含在所选择的读出放大器块中的读出放大器 。 本地驱动器根据来自第一选择线的选择信号向第二选择线施加选择信号。 只写列选择线由用于控制读出放大器的信号控制。