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1.发明授权Techniques for precision pattern transfer of carbon nanotubes from photo mask to wafers 有权碳纳米管从光掩模到晶圆的精密图案转移的技术公开(公告)号：US07538040B2
公开(公告)日：2009-05-26
申请号：US11298274
申请日：2005-12-08
申请人： Shiqun Gu , Peter G. McGrath , James Elmer , Richard J. Carter , Thomas Rueckes
发明人： Shiqun Gu , Peter G. McGrath , James Elmer , Richard J. Carter , Thomas Rueckes
IPC分类号： H01L21/461
CPC分类号： H01L21/76838 , B82Y10/00 , H01L21/32136 , H01L21/32139 , H01L51/0018 , H01L51/0048 , Y10S977/742
摘要： A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer) Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using Cl, F plasma) the portions of the hard mask which have been already partially etched away.
摘要翻译： 一种用于在晶片上图案化CNT的方法，其中CNT层设置在基板上，硬掩模膜沉积在CNT层上，BARC层（可选）涂覆在硬掩模膜上，并且抗蚀剂在 BARC层（或直接在硬掩模膜上，如果不包括BARC层）。 然后，通过蚀刻BARC层（如果提供）并且部分地蚀刻到硬掩模膜上而不是完全通过硬掩模膜（即，在到达CNT层之前停止蚀刻），将抗蚀剂图案有效地转移到硬掩模膜。然后， 剥离抗蚀剂和BARC层（如果提供），并且通过蚀刻掉（优选通过使用Cl，F等离子体）已经部分蚀刻掉的硬掩模的部分，将硬掩模图案有效地转移到CNT。
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2.发明授权Techniques for precision pattern transfer of carbon nanotubes from photo mask to wafers 失效碳纳米管从光掩模到晶圆的精密图案转移的技术公开(公告)号：US07911034B2
公开(公告)日：2011-03-22
申请号：US12471175
申请日：2009-05-22
申请人： Shiqun Gu , Peter G. McGrath , James Elmer , Richard J. Carter , Thomas Rueckes
发明人： Shiqun Gu , Peter G. McGrath , James Elmer , Richard J. Carter , Thomas Rueckes
IPC分类号： H01L29/12
CPC分类号： H01L21/76838 , B82Y10/00 , H01L21/32136 , H01L21/32139 , H01L51/0018 , H01L51/0048 , Y10S977/742
摘要： A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer). Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using C1, F plasma) the portions of the hard mask which have been already partially etched away.
摘要翻译： 一种用于在晶片上图案化CNT的方法，其中CNT层设置在基板上，硬掩模膜沉积在CNT层上，BARC层（可选）涂覆在硬掩模膜上，并且抗蚀剂在 BARC层（或直接在硬掩模膜上，如果不包括BARC层）。 然后，通过蚀刻BARC层（如果提供）并且部分地蚀刻到硬掩模膜上（而不是完全通过）硬掩模膜（即，在到达CNT层之前停止蚀刻），将抗蚀剂图案有效地转移到硬掩模膜。 然后，剥离抗蚀剂和BARC层（如果提供的话），并且通过蚀刻掉（优选使用C1，F等离子体）将硬掩模图案有效地转移到CNT上，硬掩模的已经被部分蚀刻的部分 远。
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公开(公告)号：US07915122B2
公开(公告)日：2011-03-29
申请号：US11312849
申请日：2005-12-20
申请人： Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
发明人： Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
IPC分类号： H01L21/336
CPC分类号： H01L51/0018 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0545 , Y10S977/742
摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
摘要翻译： 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层，从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。 除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层， 和纳米管层。
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4.发明授权Isolated metal plug process for use in fabricating carbon nanotube memory cells 失效用于制造碳纳米管记忆单元的隔离金属塞工艺公开(公告)号：US07884430B2
公开(公告)日：2011-02-08
申请号：US12710477
申请日：2010-02-23
IPC分类号： H01L29/84
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译： 本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。 这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。 第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。 纳米管横杆元件布置成跨越下室。 第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。 屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。 存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。
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5.发明申请ISOLATED METAL PLUG PROCESS FOR USE IN FABRICATING CARBON NANOTUBE MEMORY CELLS 失效用于制备碳纳米管存储器细胞的隔离金属压片方法公开(公告)号：US20100148277A1
公开(公告)日：2010-06-17
申请号：US12710477
申请日：2010-02-23
IPC分类号： H01L27/112
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译： 本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。 这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。 第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。 纳米管横杆元件布置成跨越下室。 第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。 屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。 存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。
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6.发明授权Isolated metal plug process for use in fabricating carbon nanotube memory cells 有权用于制造碳纳米管记忆单元的隔离金属塞工艺公开(公告)号：US07824946B1
公开(公告)日：2010-11-02
申请号：US11429069
申请日：2006-05-05
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译： 本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。 这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。 第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。 纳米管横杆元件布置成跨越下室。 第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。 屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。 存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。
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7.发明授权Programmable current-limited voltage buffer, integrated-circuit device and method for current-limiting a memory element 有权可编程限流电压缓冲器，用于限流存储器元件的集成电路器件和方法公开(公告)号：US08681579B2
公开(公告)日：2014-03-25
申请号：US13384885
申请日：2010-04-30
IPC分类号： G11C8/00
CPC分类号： G11C7/12 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/0069 , G11C27/005 , G11C27/024 , G11C2013/0073 , G11C2013/0078
摘要： A programmable current-limited voltage buffer. The programmable current-limited voltage buffer includes at least one current-bias circuit, an inverter, a write-current set control circuit, and an adaptive current limiter. The inverter is coupled to the current-bias circuit and a reference-voltage source, and is configured to couple a row line to either the current-bias circuit, or the reference-voltage source, in response to an input signal. The adaptive current limiter is coupled to the current-bias circuit and to the write-current set control circuit, and is configured to limit current flowing through the memory element in a write operation. An integrated circuit device is also provided, along with a method for current limiting a memory element during switching in an array of memory elements.
摘要翻译： 可编程限流电压缓冲器。 可编程限流电压缓冲器包括至少一个电流偏置电路，反相器，写入电流控制电路和自适应限流器。 反相器耦合到电流偏置电路和参考电压源，并且被配置为响应于输入信号将行线耦合到电流偏置电路或参考电压源。 自适应限流器耦合到电流偏置电路和写入电流设置控制电路，并且被配置为在写入操作中限制流过存储器元件的电流。 还提供了一种集成电路器件，以及用于在切换存储元件阵列期间电流限制存储器元件的方法。
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8.发明申请PASSIVATING POINT DEFECTS IN HIGH-K GATE DIELECTRIC LAYERS DURING GATE STACK FORMATION 有权栅格堆叠形成过程中高K栅介质层的钝点缺陷公开(公告)号：US20130267086A1
公开(公告)日：2013-10-10
申请号：US13439016
申请日：2012-04-04
申请人： Elke Erben , Martin Trentzsch , Richard J. Carter
发明人： Elke Erben , Martin Trentzsch , Richard J. Carter
CPC分类号： H01L29/517 , H01L21/02181 , H01L21/022 , H01L21/0228 , H01L21/28194 , H01L21/2822 , H01L29/513
摘要： Generally, the present disclosure is directed to techniques for improving the reliability of semiconductor devices with high-k gate dielectric layers by passivating point defects during the gate stack formation. One illustrative method disclosed herein includes performing a plurality of material deposition cycles to form a high-k dielectric layer above a semiconductor material layer, and introducing a passivating material into a gaseous precursor that is used for forming the high-k dielectric layer during at least one of the plurality of material deposition cycles.
摘要翻译： 通常，本公开涉及用于通过在栅极堆叠形成期间的钝化点缺陷来提高具有高k栅极电介质层的半导体器件的可靠性的技术。 本文公开的一种说明性方法包括执行多个材料沉积循环以在半导体材料层上方形成高k电介质层，以及将钝化材料引入到用于在至少形成高k介电层的气态前体中 多个材料沉积循环中的一个。
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公开(公告)号：US08095803B1
公开(公告)日：2012-01-10
申请号：US11684534
申请日：2007-03-09
申请人： Richard J. Carter , Mark S. Miller , Alan H. Karp
发明人： Richard J. Carter , Mark S. Miller , Alan H. Karp
CPC分类号： G06F21/6245
摘要： A storage manager provides data privacy, while preserving the benefits provided by existing hash based storage systems. Each file is assigned a unique identifying code. Hashes of the content-derived chunks of the file are calculated based on the content of the chunk and the code identifying the file. When a request to store a chunk of data is received, it is determined whether a chunk associated with the hash has already been stored. Because hashes are based on privacy-preserving codes as well as content, chunks of duplicate copies of a file need not be stored multiple times, and yet privacy is preserved for content at a file level. In other embodiments, hashes indicating whether a given file is public and/or indicating the identity of the requesting user are also sent with storage requests. These additional hashes enable more robust transmission and storage efficiency, while still preserving privacy.
摘要翻译： 存储管理器提供数据隐私，同时保留现有基于哈希的存储系统提供的优点。 每个文件都被分配一个唯一的识别码。 基于块的内容和识别文件的代码来计算文件的内容导出块的哈希。 当接收到存储数据块的请求时，确定是否已经存储与散列相关联的块。 由于哈希是基于隐私保护代码以及内容，文件的重复副本的块不需要多次存储，而是保留文件级内容的隐私。 在其他实施例中，指示给定文件是公开的和/或指示请求用户的身份的散列也与存储请求一起发送。 这些额外的哈希可以实现更强大的传输和存储效率，同时保持隐私。
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10.发明授权Integrated circuit long and short channel metal gate devices and method of manufacture 有权集成电路长短通道金属栅极器件及其制造方法公开(公告)号：US07723192B2
公开(公告)日：2010-05-25
申请号：US12048414
申请日：2008-03-14
IPC分类号： H01L21/8234
CPC分类号： H01L21/823456 , H01L21/28114 , H01L21/823468 , H01L29/4933 , H01L29/66545
摘要： A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench.
摘要翻译： 提供了一种用于制造集成电路的方法，该集成电路包括短沟道（SC）器件和每个由层间电介质覆盖的长沟道（LC）器件。 SC器件具有SC栅极堆叠，LC器件最初具有虚拟栅极。 在一个实施例中，该方法包括以下步骤：去除伪栅极以形成LC器件沟槽，以及在SC器件和LC器件上沉积金属栅极材料。 金属栅极材料接触SC栅极堆叠并且基本上填充LC器件沟槽。
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