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公开(公告)号：US08004367B2
公开(公告)日：2011-08-23
申请号：US12428215
申请日：2009-04-22
IPC分类号： H03B5/12
摘要： A PLL receives an indicator indicating that it is to operate at a different operating frequency than a current operating frequency. A control word is selected from a set of linear control words based upon the different operating frequency. A capacitance of a variable capacitor of a voltage-controlled oscillator is adjusted based upon the control word. The variable capacitor is monotonic and non-linear relative to the set of linear control words.
摘要翻译： 一个PLL接收一个指示器，指示它在与当前工作频率不同的工作频率下工作。 基于不同的操作频率从一组线性控制字中选择控制字。 基于控制字调整压控振荡器的可变电容器的电容。 可变电容器相对于线性控制字的集合是单调的和非线性的。
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公开(公告)号：US20100271137A1
公开(公告)日：2010-10-28
申请号：US12428215
申请日：2009-04-22
IPC分类号： H03L7/00
摘要： A PLL receives an indicator indicating that it is to operate at a different operating frequency than a current operating frequency. A control word is selected from a set of linear control words based upon the different operating frequency. A capacitance of a variable capacitor of a voltage-controlled oscillator is adjusted based upon the control word. The variable capacitor is monotonic and non-linear relative to the set of linear control words.
摘要翻译： 一个PLL接收一个指示器，指示它在与当前工作频率不同的工作频率下工作。 基于不同的操作频率从一组线性控制字中选择控制字。 基于控制字调整压控振荡器的可变电容器的电容。 可变电容器相对于线性控制字的集合是单调的和非线性的。
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公开(公告)号：US08442472B2
公开(公告)日：2013-05-14
申请号：US13079516
申请日：2011-04-04
申请人： Haolu Xie , Manish N. Shah
发明人： Haolu Xie , Manish N. Shah
CPC分类号： H03K23/662
摘要： A frequency divider with a twenty-five percent duty cycle is disclosed. A frequency divider may include an input configured to receive a clock signal, each cycle of the clock signal including a first phase and a second phase, a plurality of latches, and a plurality of three-state circuits wherein a first of the plurality of three-state circuits is configured to drive a first twenty-five percent duty cycle signal from within the first three-state circuit high during a first phase of a first of two clock cycles.
摘要翻译： 公开了一种具有25％占空比的分频器。 分频器可以包括被配置为接收时钟信号的输入，时钟信号的每个周期包括第一相位和第二相位，多个锁存器以及多个三态电路，其中多个三态中的第一个 - 状态电路被配置为在两个时钟周期中的第一个时钟周期的第一阶段期间将来自第一三态电路内的第二个25％的占空比信号驱动为高电平。
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公开(公告)号：US20120252396A1
公开(公告)日：2012-10-04
申请号：US13078502
申请日：2011-04-01
申请人： Haolu Xie , Manish N. Shah , Patrick L. Rakers
发明人： Haolu Xie , Manish N. Shah , Patrick L. Rakers
CPC分类号： H04B1/28 , H03D2200/0074 , H03D2200/0088 , H03K2217/0054
摘要： A technique for improving the linearity of a mixer is disclosed. A converter may include a mixer comprising a first metal-oxide semiconductor field-effect transistor (MOSFET) having a gate, a first conducting terminal coupled to an input of the converter, and a second conducting terminal coupled to an output of the converter, and a mixer driver having a first output coupled to the gate of the first MOSFET, the mixer driver configured to receive a local-oscillator signal having a first phase and a second phase, drive the first MOSFET off during the first phase of the local-oscillator signal, drive the first MOSFET on for a first period of time in response to a transition from the first phase of the local-oscillator signal to the second phase of the local-oscillator signal, and force the gate of the first MOSFET into a high impedance state for a second period of time during the second phase of the local-oscillator signal and after the expiration of the first period of time.
摘要翻译： 公开了一种改善混频器线性度的技术。 A转换器可以包括混合器，其包括具有栅极的第一金属氧化物半导体场效应晶体管（MOSFET），耦合到转换器的输入端的第一导电端子和耦合到转换器的输出端的第二导通端子，以及 混频器驱动器，其具有耦合到第一MOSFET的栅极的第一输出，混频器驱动器被配置为接收具有第一相位和第二相位的本地振荡器信号，在本机振荡器的第一阶段期间驱动第一MOSFET关断 信号，响应于从本地振荡器信号的第一相到本地振荡器信号的第二相的转变，驱动第一MOSFET导通第一时间段，并迫使第一MOSFET的栅极变为高电平 在本地振荡器信号的第二阶段期间和在第一时间段到期之后的第二时间段的阻抗状态。
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5.发明授权Differential transmission line shielded by two or more spaced groups of shields 有权差分传输线由两个或更多间隔的屏蔽组屏蔽公开(公告)号：US08922291B2
公开(公告)日：2014-12-30
申请号：US13467447
申请日：2012-05-09
申请人： Haolu Xie , Chi-Taou Tsai , Patrick L. Rakers
发明人： Haolu Xie , Chi-Taou Tsai , Patrick L. Rakers
IPC分类号： H05K1/02
CPC分类号： H05K1/0219 , H01L23/5225 , H01L2924/0002 , H01P3/02 , H01R13/6461 , H05K1/0245 , Y10T29/49117 , H01L2924/00
摘要： A shield for differential transmission lines formed in a first metal layer may include one or more floating shields, each floating shield comprising an upper-side tile formed in a second metal layer of the integrated circuit adjacent to the first metal layer, a lower-side tile formed in a third metal layer of the integrated circuit adjacent to the first metal layer and non-adjacent to the second metal layer, and at least one via configured to electrically couple the upper-side tile at an end of the length of the upper-side tile to the lower-side tile and at an end of the length of the lower-side tile.
摘要翻译： 形成在第一金属层中的差分传输线的屏蔽可以包括一个或多个浮动屏蔽，每个浮动屏蔽包括形成在与第一金属层相邻的集成电路的第二金属层中的上侧瓦，下侧 在与所述第一金属层相邻并且不与所述第二金属层相邻的所述集成电路的第三金属层中形成的至少一个通孔，以及至少一个通孔，其构造成在所述上部的所述长度的末端的末端电连接所述上侧瓦 并且在下侧瓦片的长度的末端。
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公开(公告)号：US20130300514A1
公开(公告)日：2013-11-14
申请号：US13467447
申请日：2012-05-09
申请人： Haolu Xie , Chi-Taou Tsai , Patrick L. Rakers
发明人： Haolu Xie , Chi-Taou Tsai , Patrick L. Rakers
CPC分类号： H05K1/0219 , H01L23/5225 , H01L2924/0002 , H01P3/02 , H01R13/6461 , H05K1/0245 , Y10T29/49117 , H01L2924/00
摘要： A shield for differential transmission lines formed in a first metal layer may include one or more floating shields, each floating shield comprising an upper-side tile formed in a second metal layer of the integrated circuit adjacent to the first metal layer, a lower-side tile formed in a third metal layer of the integrated circuit adjacent to the first metal layer and non-adjacent to the second metal layer, and at least one via configured to electrically couple the upper-side tile at an end of the length of the upper-side tile to the lower-side tile and at an end of the length of the lower-side tile.
摘要翻译： 形成在第一金属层中的差分传输线的屏蔽可以包括一个或多个浮动屏蔽，每个浮动屏蔽包括形成在与第一金属层相邻的集成电路的第二金属层中的上侧瓦，下侧 在与所述第一金属层相邻并且不与所述第二金属层相邻的所述集成电路的第三金属层中形成的至少一个通孔，以及至少一个通孔，其构造成在所述上部的所述长度的末端的末端电连接所述上侧瓦 并且在下侧瓦片的长度的末端。
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公开(公告)号：US08493127B1
公开(公告)日：2013-07-23
申请号：US13419150
申请日：2012-03-13
申请人： Chuanzhao Yu , Haolu Xie , Dave Newman
发明人： Chuanzhao Yu , Haolu Xie , Dave Newman
IPC分类号： G06F7/44
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1491 , H03D2200/0023
摘要： A mixer may include a linearization circuit. The linearization circuit may include and operation amplifier, a first pass device, a second pass device, a first feedback resistor, and a second feedback resistor. Each of the first pass device and the second pass device may have a gate terminal, a first non-gate terminal, and a second non-gate terminal and coupled to its gate terminal to an output terminal of the operational amplifier and configured to be coupled at its first non-gate terminal to a high potential source. Each of the first feedback resistor and the second feedback resistor may have a first terminal and a second terminal, the first terminal coupled to the positive input terminal of the operational amplifier and the second terminal coupled to the second non-gate terminal of an associated pass device and the positive polarity of the differential baseband output.
摘要翻译： 混频器可以包括线性化电路。 线性化电路可以包括运算放大器，第一通道器件，第二通路器件，第一反馈电阻器和第二反馈电阻器。 第一通过器件和第二通过器件中的每一个可以具有栅极端子，第一非栅极端子和第二非栅极端子，并且连接到其栅极端子到运算放大器的输出端子并被配置为耦合 在其第一个非门极端到高电位源。 第一反馈电阻器和第二反馈电阻器中的每个可以具有第一端子和第二端子，第一端子耦合到运算放大器的正输入端子，而第二端子耦合到相关通道的第二非门极端子 器件和差分基带输出的正极性。
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公开(公告)号：US20120252393A1
公开(公告)日：2012-10-04
申请号：US13079516
申请日：2011-04-04
申请人： Haolu Xie , Manish N. Shah
发明人： Haolu Xie , Manish N. Shah
CPC分类号： H03K23/662
摘要： A frequency divider with a twenty-five percent duty cycle is disclosed. A frequency divider may include an input configured to receive a clock signal, each cycle of the clock signal including a first phase and a second phase, a plurality of latches, and a plurality of three-state circuits wherein a first of the plurality of three-state circuits is configured to drive a first twenty-five percent duty cycle signal from within the first three-state circuit high during a first phase of a first of two clock cycles.
摘要翻译： 公开了一种具有25％占空比的分频器。 分频器可以包括被配置为接收时钟信号的输入，时钟信号的每个周期包括第一相位和第二相位，多个锁存器以及多个三态电路，其中多个三态中的第一个 - 状态电路被配置为在两个时钟周期中的第一个时钟周期的第一阶段期间将来自第一三态电路内的第二个25％的占空比信号驱动为高电平。
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公开(公告)号：US08364112B2
公开(公告)日：2013-01-29
申请号：US13078502
申请日：2011-04-01
申请人： Haolu Xie , Manish N. Shah , Patrick L. Rakers
发明人： Haolu Xie , Manish N. Shah , Patrick L. Rakers
IPC分类号： H04B1/16
CPC分类号： H04B1/28 , H03D2200/0074 , H03D2200/0088 , H03K2217/0054
摘要： A technique for improving the linearity of a mixer is disclosed. A converter may include a mixer comprising a first metal-oxide semiconductor field-effect transistor (MOSFET) having a gate, a first conducting terminal coupled to an input of the converter, and a second conducting terminal coupled to an output of the converter, and a mixer driver having a first output coupled to the gate of the first MOSFET, the mixer driver configured to receive a local-oscillator signal having a first phase and a second phase, drive the first MOSFET off during the first phase of the local-oscillator signal, drive the first MOSFET on for a first period of time in response to a transition from the first phase of the local-oscillator signal to the second phase of the local-oscillator signal, and force the gate of the first MOSFET into a high impedance state for a second period of time during the second phase of the local-oscillator signal and after the expiration of the first period of time.
摘要翻译： 公开了一种改善混频器线性度的技术。 A转换器可以包括混合器，其包括具有栅极的第一金属氧化物半导体场效应晶体管（MOSFET），耦合到转换器的输入端的第一导电端子和耦合到转换器的输出端的第二导通端子，以及 混频器驱动器，其具有耦合到第一MOSFET的栅极的第一输出，混频器驱动器被配置为接收具有第一相位和第二相位的本地振荡器信号，在本机振荡器的第一阶段期间驱动第一MOSFET关断 信号，响应于从本地振荡器信号的第一相到本地振荡器信号的第二相的转变，驱动第一MOSFET导通第一时间段，并迫使第一MOSFET的栅极变为高电平 在本地振荡器信号的第二阶段期间和在第一时间段期满之后的第二时间段的阻抗状态。
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