公开(公告)号：US4085595A

公开(公告)日：1978-04-25

申请号：US752661

申请日：1976-12-20

申请人： Shozo Saito ,  Naoyuki Inoue

发明人： Shozo Saito ,  Naoyuki Inoue

IPC分类号： F25B15/00 ,  F25B33/00

CPC分类号： F25B15/008 ,  F25B33/00 ,  Y02B30/62

摘要： A double effect absorption system having improved thermal efficiency is provided wherein a part of a weak solution fed from an absorber to a high pressure or first generator is bypassed to a second generator and the bypassed solution is transferred with the heat energy from refrigerant passed through a tube within a low pressure or second generator.

摘要翻译： 提供了具有提高的热效率的双效吸收系统，其中从吸收器供给高压或第一发生器的弱溶液的一部分被旁路到第二发生器，并且旁路溶液以来自制冷剂的热能被转移通过 管在低压或第二发电机内。

公开(公告)号：US4472947A

公开(公告)日：1984-09-25

申请号：US438261

申请日：1982-11-01

申请人： Shozo Saito ,  Naoyuki Inoue ,  Toshihiro Okuda

发明人： Shozo Saito ,  Naoyuki Inoue ,  Toshihiro Okuda

IPC分类号： F25B15/00 ,  F25B15/06 ,  F25B49/04

CPC分类号： F25B49/043 ,  F25B15/06 ,  Y02B30/62

摘要： An absorption refrigerating system is provided wherein the total circulation flow rate of a diluted solution (absorbing liquid) by pumps is adjustable according to the measured change in the refrigerating load so that the flow rate of the diluted solution is kept at desirable levels to balance with changing refrigerating load.

摘要翻译： 提供了一种吸收式制冷系统，其中通过泵的稀释溶液（吸收液体）的总循环流量根据所测量的制冷负荷的变化是可调节的，使得稀释溶液的流量保持在期望的水平以与 改变制冷负荷。

公开(公告)号：US4183228A

公开(公告)日：1980-01-15

申请号：US886571

申请日：1978-03-14

申请人： Shozo Saito ,  Naoyuki Inoue

发明人： Shozo Saito ,  Naoyuki Inoue

IPC分类号： F25B15/00 ,  F25B33/00

CPC分类号： F25B15/008 ,  Y02B30/62

摘要： A double effect absorption refrigerating system having improved thermal efficiency is provided wherein a solution concentrated by a high pressure generator is, after being used to raise the temperature of a weak solution fed to the high pressure generator and before being fed into a low pressure generator, heated with heat energy transferred thereto from a refrigerant passed through a tube within the low pressure generator.

摘要翻译： 提供一种具有提高的热效率的双效吸收式制冷系统，其中由高压发生器浓缩的溶液在用于提高供给高压发生器的弱溶液的温度并且在被供给到低压发生器之前， 用从低压发生器内通过管的制冷剂转移到其上的热能加热。

公开(公告)号：US5995442A

公开(公告)日：1999-11-30

申请号：US236832

申请日：1999-01-25

申请人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

发明人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/04 ,  G11C11/407 ,  G11C11/41 ,  G11C11/413 ,  H01L27/10 ,  G06F13/16

CPC分类号： G11C7/1072 ,  G11C7/1018 ,  G11C7/22

摘要： A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled.

摘要翻译： 半导体存储器件包括存储单元组，所述存储单元组包括排列成矩阵的多个存储器单元; 指定电路，用于依次指定存储器单元中由连续地址寻址的存储器单元，并将其输入激活状态; 用于对由指定电路指定的连续存储单元进行数据读出/写入操作（数据I / O操作）的数据输入/输出（I / O）电路，该控制基于读出/ 从外部部分提供的写入信号; 用于对从外部提供的基本时钟信号的周期数进行计数的计数器电路; 以及控制器，用于接收从外部部分提供的至少一个或多个指定信号，用于每个指定信号输出用于指定特定周期的控制信号作为开始周期，以对基本时钟信号的周期数进行计数，并且 指示计数器电路基于控制信号对基本时钟信号的计数数进行计数，并控制由指定电路执行的指定操作和数据I / O电路的数据I / O操作，使得存储器 对存储单元组的访问操作进行控制。

公开(公告)号：US5612925A

公开(公告)日：1997-03-18

申请号：US463394

申请日：1995-06-05

申请人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

发明人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/04 ,  G11C11/407 ,  G11C11/41 ,  G11C11/413 ,  H01L27/10

CPC分类号： G11C7/1072 ,  G11C7/1018 ,  G11C7/22

摘要： A semiconductor memory device, including a memory cell array having a plurality of memory cells arranged in rows and columns, the memory cells storing data and being selected according to address signals. The device includes a control unit which receives a clock signal and a first control, or trigger, signal for outputting a plurality of the data in synchronism with the clock signal after the first control signal is asserted. The output of the data beginning after a number of clock cycles (N) of the clock signal (N being a positive integer .gtoreq.2) after the first control signal is asserted, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output.

摘要翻译： 一种半导体存储器件，包括具有以行和列排列的多个存储单元的存储单元阵列，存储单元存储数据并根据地址信号进行选择。 该装置包括控制单元，该控制单元接收时钟信号和用于在第一控制信号被断言之后与时钟信号同步地输出多个数据的第一控制或触发信号。 在第一控制信号被断言之后的时钟信号（N为正整数> / = 2）的多个时钟周期（N）之后开始的数据的输出，在每个 在输出开始直到输出多个数据之后的时钟周期。

公开(公告)号：US5323358A

公开(公告)日：1994-06-21

申请号：US024354

申请日：1993-03-01

申请人： Haruki Toda ,  Yuji Watanabe ,  Hitoshi Kuyama ,  Shozo Saito

发明人： Haruki Toda ,  Yuji Watanabe ,  Hitoshi Kuyama ,  Shozo Saito

IPC分类号： G11C11/407 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C11/41 ,  H01L27/10 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C8/18 ,  G11C7/22

摘要： A method for accessing a clock-synchronous semiconductor memory device including memory cells arranged in matrix. The cells are divided into at least two blocks, access to the cells in these blocks is designated from address data provided from an external device, and access to the memory cell is executed synchronously with an externally-supplied clock signal, which comprises setting the other blocks in an access preparation state or in an access operation standby state while one block is in an access operating state, setting a certain block in the access operating state via the access preparation state when the certain block is designated for the access operation by the address data and if the certain block is in the access operating state, and setting a certain block in the access operating state immediately when the certain block is designated for the access operation by the address data and if the certain block is in the access preparation state or in the access operation standby state. In the device, the designation of the cell in the block to be accessed is set using address data designating a block externally-provided from outside of the device.

摘要翻译： 一种用于访问包括以矩阵布置的存储单元的时钟同步半导体存储器件的方法。 单元被划分为至少两个块，从外部设备提供的地址数据指定对这些块中的单元的访问，并且与外部提供的时钟信号同步地执行对存储单元的访问，其中包括设置另一个 在一个块处于访问操作状态时处于访问准备状态或访问操作待机状态的块，当通过地址指定特定块进行访问操作时，经由访问准备状态将某个块设置在访问操作状态 数据，并且如果某个块处于访问操作状态，并且当特定块被地址数据指定用于访问操作时，并且特定块处于访问准备状态时，立即将某个块设置在访问操作状态，或者 在访问操作待机状态。 在设备中，使用指定从设备外部提供的块的地址数据来设置要访问的块中的小区的指定。

公开(公告)号：US5119337A

公开(公告)日：1992-06-02

申请号：US509212

申请日：1990-04-16

申请人： Mitsuru Shimizu ,  Syuso Fujii ,  Shozo Saito

发明人： Mitsuru Shimizu ,  Syuso Fujii ,  Shozo Saito

IPC分类号： G01R31/28 ,  G11C5/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50 ,  H01L21/66 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C29/50 ,  G11C5/145 ,  G11C5/146 ,  G11C8/08 ,  G06F2201/81 ,  G11C11/401

摘要： A semiconductor memory device such as dynamic random access memories comprises a work line drive circuit provided with two MOS transistors and a word line to which a word line drive signal is supplied, a substrate bias generation circuit for applying a bias voltage to a semiconductor substrate for MOS transistors, a burn-in mode detection circuit for detecting a burn-in test mode signal, and a substrate bias control circuit for controlling the substrate bias generation circuit. When the semiconductor memory device is subjected to a burn-in test, the power supply level Vcc is increased to raise the voltage of the word line drive signal as compared to that at a normal operation. Accordingly, a high level word line drive signal will be applied to cell transistors, thereby performing correct screening thereof.

公开(公告)号：US5343425A

公开(公告)日：1994-08-30

申请号：US25564

申请日：1993-03-03

申请人： Shozo Saito ,  Haruki Toda

发明人： Shozo Saito ,  Haruki Toda

IPC分类号： G06F12/04 ,  G06F12/00 ,  G06F12/06 ,  G06T1/60 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C19/28

CPC分类号： G11C7/1075

摘要： A semiconductor memory device has a memory cell array including many memory cells, a first data I/O section for implementing random input and output of data for the memory cells based on an externally-supplied random I/O signal, a second data I/O section for implementing serial input and output of data for the memory cells, a counter for counting the number of externally-supplied basic clock signal cycles, a controller for controlling the I/O of data for the memory cells in accordance with the number of the cycles of basic clock signals. The counter is capable of inputting at least one kind of externally-supplied designation signals, generating a designation control signal for designating a specified cycle which is a count starting cycle for the basic clock signal at each designation signals, generating instructions for commencement of count for the number of cycles of the basic clock signal in the counter based on the designated control signal, and synchronously controlling designation of addresses based on the number of cycles counted by the counter and the I/O operations of the first data I/O means and the second data I/O means from the specified cycle of the designated basic clock signal.

摘要翻译： 半导体存储器件具有包括许多存储单元的存储单元阵列，第一数据I / O部分，用于根据外部提供的随机I / O信号来实现用于存储器单元的数据的随机输入和输出;第二数据I / O部分，用于实现存储器单元的数据的串行输入和输出，用于对外部提供的基本时钟信号周期的数量进行计数的计数器，用于根据存储器单元的数量控制存储器单元的数据的I / O的控制器 基本时钟信号的周期。 计数器能够输入至少一种外部提供的指定信号，产生用于指定作为每个指定信号的基本时钟信号的计数开始周期的指定周期的指定控制信号，生成用于开始计数的指令 基于所指定的控制信号的计数器中的基本时钟信号的周期数，并且基于由计数器计数的周期数和第一数据I / O装置的I / O操作来同步地控制地址的指定，以及 第二数据I / O表示从指定的基本时钟信号的指定周期。

公开(公告)号：US5313437A

公开(公告)日：1994-05-17

申请号：US775602

申请日：1991-10-15

申请人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

发明人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/04 ,  G11C11/407 ,  G11C11/41 ,  G11C11/413 ,  H01L27/10 ,  G11C14/00

CPC分类号： G11C7/1072 ,  G11C7/1018 ,  G11C7/22

摘要： A semiconductor memory device including a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying a plurality of memory cells addressed by sequential addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number in response to cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles in response to the basic clock signal, and for instructing the counter circuit to count the number of cycles in response to the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit in accordance with the number of cycles in response to the basic clock.

摘要翻译： 一种半导体存储器件，包括：存储单元组，包括以矩阵形式布置的多个存储单元; 指定电路，用于指定存储器单元中的顺序地址寻址的多个存储单元，并将其输入到活动状态; 一个数据输入/输出（I / O）电路，用于在基于读出/写入的控制下执行由指定电路指定的存储单元的数据读出/写入操作（数据I / O操作） - 从外部提供的信号; 计数器电路，用于响应于从外部提供的基本时钟信号的周期来对所述数量进行计数; 以及控制器，用于接收从外部部分提供的至少一个或多个指定信号，用于输出用于指定特定周期的每个指定信号的控制信号作为响应于基本时钟信号对周期数进行计数的起始周期， 并且用于指示计数器电路根据控制信号对基本时钟信号进行响应的周期数进行计数，并且用于控制由指定电路执行的指定操作和数据I / O电路的数据I / O操作 根据响应于基本时钟的周期数。

公开(公告)号：US4994874A

公开(公告)日：1991-02-19

申请号：US425950

申请日：1989-10-24

申请人： Mitsuru Shimizu ,  Yoshio Okada ,  Syuso Fujii ,  Shozo Saito

发明人： Mitsuru Shimizu ,  Yoshio Okada ,  Syuso Fujii ,  Shozo Saito

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02

CPC分类号： H01L27/0259

摘要： First to third N.sup.+ -type impurity regions are formed separately from one another by a preset distance in the surface area of a P-type semiconductor substrate or a P-well region formed in an N-type semiconductor substrate. The first impurity region is connected to a power source and the second impurity region is connected to a ground terminal. The third impurity region formed between the first and second impurity regions is connected to one end of an input protection resistor which is connected at the other end to a signal input pad. The first impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the first and third impurity regions constitute a first bipolar transistor for input protection and the second impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the second and third impurity regions constitute a second bipolar transistor for input protection. The resistor and the first and second bipolar transistors constitute an input protection circuit.

摘要翻译： 在N型半导体衬底中形成的P型半导体衬底或P阱区域的表面区域中，第一至第三N +型杂质区彼此分开地预定距离地形成。 第一杂质区域连接到电源，第二杂质区域连接到接地端子。 形成在第一和第二杂质区域之间的第三杂质区域连接到另一端连接到信号输入焊盘的输入保护电阻器的一端。 位于第一和第三杂质区域之间的第一杂质区域，第三杂质区域和P型半导体衬底或P阱区域的部分构成用于输入保护的第一双极晶体管，第二杂质区域，第三杂质区域 位于第二和第三杂质区之间的P型半导体衬底或P阱区的部分构成用于输入保护的第二双极晶体管。 电阻器和第一和第二双极晶体管构成输入保护电路。