公开(公告)号：US07420250B2

公开(公告)日：2008-09-02

申请号：US11212000

申请日：2005-08-25

申请人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

发明人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

IPC分类号： H01L23/62

CPC分类号： H01L27/0255

摘要： Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.

摘要翻译： 提供一种静电放电（ESD）保护装置及其制造方法。 在一个示例中，ESD保护装置包括形成在衬底中的齐纳二极管区域和邻近齐纳二极管区域形成的N型金属氧化物半导体（NMOS）器件。 齐纳二极管区域具有两个掺杂区域，位于两个掺杂区域之间的接地电位的栅极和在衬底中形成的两个光掺杂漏极（LDD）特征。 LDD特征之一位于两个掺杂区域和栅极之间。 NMOS器件包括形成在衬底中的源极和漏极，以及位于源极和漏极之间的第二栅极。

公开(公告)号：US20060043491A1

公开(公告)日：2006-03-02

申请号：US11212000

申请日：2005-08-25

申请人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

发明人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

IPC分类号： H01L23/62

CPC分类号： H01L27/0255

摘要： Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.

摘要翻译： 提供一种静电放电（ESD）保护装置及其制造方法。 在一个示例中，ESD保护装置包括形成在衬底中的齐纳二极管区域和邻近齐纳二极管区域形成的N型金属氧化物半导体（NMOS）器件。 齐纳二极管区域具有两个掺杂区域，位于两个掺杂区域之间的接地电位的栅极和在衬底中形成的两个光掺杂漏极（LDD）特征。 LDD特征之一位于两个掺杂区域和栅极之间。 NMOS器件包括形成在衬底中的源极和漏极，以及位于源极和漏极之间的第二栅极。

公开(公告)号：US20070159754A1

公开(公告)日：2007-07-12

申请号：US11332565

申请日：2006-01-12

申请人： Shao-Chang Huang ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jiaw-Ren Shih

发明人： Shao-Chang Huang ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jiaw-Ren Shih

IPC分类号： H02H3/22

CPC分类号： H01L27/0266 ,  H01L27/0255

摘要： A circuit system is disclosed for protecting a capacitor coupled between a voltage supply node and a complementary voltage supply node from an ESD. The circuit system includes at least one NMOS transistor having a drain coupled to the voltage supply node, a source and a gate together coupled to the complementary voltage supply node, and at least one diode chain having one or more diodes serially coupled between the voltage supply node and the complementary voltage supply node. During an ESD event, the diode chain and the NMOS transistor dissipate an ESD current from the voltage supply node to the complementary voltage supply node, thereby protecting the capacitor from ESD induced damages.

摘要翻译： 公开了一种用于保护耦合在电压供应节点和互补电压供应节点之间的电容器与ESD的电路系统。 电路系统包括至少一个NMOS晶体管，其具有耦合到电压供应节点的漏极，一起耦合到互补电源节点的源极和至少一个二极管链，其具有串联耦合在电压源之间的一个或多个二极管 节点和互补电源节点。 在ESD事件期间，二极管链和NMOS晶体管消耗从电压供应节点到互补电源节点的ESD电流，从而保护电容器免受ESD引起的损坏。

公开(公告)号：US07420793B2

公开(公告)日：2008-09-02

申请号：US11332565

申请日：2006-01-12

申请人： Shao-Chang Huang ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jiaw-Ren Shih

发明人： Shao-Chang Huang ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jiaw-Ren Shih

IPC分类号： H02H9/00

CPC分类号： H01L27/0266 ,  H01L27/0255

摘要： A circuit system is disclosed for protecting a capacitor coupled between a voltage supply node and a complementary voltage supply node from an ESD. The circuit system includes at least one NMOS transistor having a drain coupled to the voltage supply node, a source and a gate together coupled to the complementary voltage supply node, and at least one diode chain having one or more diodes serially coupled between the voltage supply node and the complementary voltage supply node. During an ESD event, the diode chain and the NMOS transistor dissipate an ESD current from the voltage supply node to the complementary voltage supply node, thereby protecting the capacitor from ESD induced damages.

摘要翻译： 公开了一种用于保护耦合在电压供应节点和互补电压供应节点之间的电容器与ESD的电路系统。 电路系统包括至少一个NMOS晶体管，其具有耦合到电压供应节点的漏极，一起耦合到互补电源节点的源极和至少一个二极管链，其具有串联耦合在电压源之间的一个或多个二极管 节点和互补电源节点。 在ESD事件期间，二极管链和NMOS晶体管消耗从电压供应节点到互补电源节点的ESD电流，从而保护电容器免受ESD引起的损坏。

公开(公告)号：US07465994B2

公开(公告)日：2008-12-16

申请号：US11512850

申请日：2006-08-29

申请人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

发明人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of the first conductive gate layer. The third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode for enhancing dissipation of ESD current during a negative ESD event.

摘要翻译： ESD保护电路的布局结构包括：第一MOS器件区域，具有设置在第一导电栅极层的两侧的具有相同极性的第一和第二掺杂区域;以及第三掺杂区域，沿第一掺杂区域设置在一侧 的第一导电栅极层。 第三掺杂区域具有与第一和第二掺杂区域不同的极性，使得第三掺杂区域和第二掺杂区域形成用于在负ESD事件期间增强ESD电流的耗散的二极管。

公开(公告)号：US20060284256A1

公开(公告)日：2006-12-21

申请号：US11157200

申请日：2005-06-17

申请人： Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： The present invention provides a layout structure for an electrostatic discharge (ESD) protection circuit. The layout structure includes a first MOS device area, a second MOS device area, and a doped region. The first MOS device area has at least one source/drain region of a first polarity type. The second MOS device, which is adjacent to the first MOS device area, has at least one source/drain region of the first polarity type. A doped region of a second polarity type is interposed between the source/drain region of the first MOS device and the source/drain region of the second MOS device, such that the doped region and the source/drain regions interfacing therewith forming one or more diodes for dissipating ESD charges during an ESD event.

摘要翻译： 本发明提供了一种用于静电放电（ESD）保护电路的布局结构。 布局结构包括第一MOS器件区域，第二MOS器件区域和掺杂区域。 第一MOS器件区域具有至少一个第一极性类型的源极/漏极区域。 与第一MOS器件区域相邻的第二MOS器件具有至少一个第一极性类型的源极/漏极区域。 第二极性类型的掺杂区介于第一MOS器件的源极/漏极区域和第二MOS器件的源极/漏极区域之间，使得与其形成一个或多个的掺杂区域和源极/漏极区域 用于在ESD事件期间耗散ESD电荷的二极管。

公开(公告)号：US20060289935A1

公开(公告)日：2006-12-28

申请号：US11512850

申请日：2006-08-29

申请人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

发明人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of the first conductive gate layer. The third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode for enhancing dissipation of ESD current during a negative ESD event.

摘要翻译： ESD保护电路的布局结构包括：第一MOS器件区域，具有设置在第一导电栅极层的两侧的具有相同极性的第一和第二掺杂区域;以及第三掺杂区域，沿第一掺杂区域设置在一侧 的第一导电栅极层。 第三掺杂区域具有与第一和第二掺杂区域不同的极性，使得第三掺杂区域和第二掺杂区域形成用于在负ESD事件期间增强ESD电流的耗散的二极管。

公开(公告)号：US20080042207A1

公开(公告)日：2008-02-21

申请号：US11506948

申请日：2006-08-17

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Kuo-Feng Yu ,  C.S. Tang ,  Cheng-Chun Ting

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Kuo-Feng Yu ,  C.S. Tang ,  Cheng-Chun Ting

IPC分类号： H01L23/62

CPC分类号： H01L23/60 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0266 ,  H01L29/41775 ,  H01L29/4238 ,  H01L2224/0401 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A transistor layout is disclosed for improving electrostatic discharge capabilities. The layout has a first gate region with a first active region and a second active region formed on two sides thereof, and a second gate region placed next to the second active region with a third active region placed on an opposing side of the second gate region from the second active region. A first and a second set of contacts formed on the first and the third active regions, and a third set of contacts formed on the second active region, wherein the third set of contacts are spaced in parallel with and offset from the other two sets of contacts such that no contact from the third set is aligned laterally with a contact from either the first or the second set of contacts.

摘要翻译： 公开了用于改善静电放电能力的晶体管布局。 布局具有第一栅极区域，其具有形成在其两侧的第一有源区和第二有源区，以及放置在第二有源区旁边的第二栅极区，第三有源区位于第二栅极区的相对侧 从第二个活跃区域。 形成在第一和第三有源区上的第一和第二组触点，以及形成在第二有源区上的第三组触点，其中第三组触点与另外两组触点间隔开并偏离 触点，使得第三组的接触不与来自第一组或第二组触点的触点对齐。

公开(公告)号：US20080174923A1

公开(公告)日：2008-07-24

申请号：US11812221

申请日：2007-06-15

申请人： Yi-Hsun Wu ,  Yan-Chih Jiang ,  Yu-Chang Lin ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Yan-Chih Jiang ,  Yu-Chang Lin ,  Jian-Hsing Lee

IPC分类号： H02H9/00 ,  H01L21/336

CPC分类号： H01L27/0255

摘要： A semiconductor device formed in a semiconductor substrate for dissipating electrostatic discharge and/or accumulated charge in an integrated circuit is provided. In one embodiment, the device comprises a semiconductor substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; and a dummy pad formed over the plurality of layers of metal lines, the dummy pad having a diode connected thereto and to ground for providing a discharge path for the electrostatic discharge and/or accumulated charge.

公开(公告)号：US20060278928A1

公开(公告)日：2006-12-14

申请号：US11152440

申请日：2005-06-14

申请人： Yi-Hsun Wu ,  Kuan-Lun Chang ,  Chuan-Ying Lee ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Kuan-Lun Chang ,  Chuan-Ying Lee ,  Jian-Hsing Lee

IPC分类号： H01L23/62

CPC分类号： H01L27/0262

摘要： A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event. The first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event.

摘要翻译： 公开了一种用于静电放电（ESD）保护电路的半导体布局结构。 半导体布局结构包括第一区域，其中构造一个或多个器件用作可控硅整流器，以及第二区域，其中构造至少一个器件用作触发源，该触发源提供触发电流 触发可控硅整流器，以在ESD事件期间耗散ESD电荷。 第一区域和第二区域彼此相邻放置，而不会在其间物理地插入或电连接电阻区域，使得在ESD事件期间由可控硅整流器接收的触发电流增加。