公开(公告)号：US20060043491A1

公开(公告)日：2006-03-02

申请号：US11212000

申请日：2005-08-25

申请人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

发明人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

IPC分类号： H01L23/62

CPC分类号： H01L27/0255

摘要： Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.

摘要翻译： 提供一种静电放电（ESD）保护装置及其制造方法。 在一个示例中，ESD保护装置包括形成在衬底中的齐纳二极管区域和邻近齐纳二极管区域形成的N型金属氧化物半导体（NMOS）器件。 齐纳二极管区域具有两个掺杂区域，位于两个掺杂区域之间的接地电位的栅极和在衬底中形成的两个光掺杂漏极（LDD）特征。 LDD特征之一位于两个掺杂区域和栅极之间。 NMOS器件包括形成在衬底中的源极和漏极，以及位于源极和漏极之间的第二栅极。

公开(公告)号：US07420250B2

公开(公告)日：2008-09-02

申请号：US11212000

申请日：2005-08-25

申请人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

发明人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

IPC分类号： H01L23/62

CPC分类号： H01L27/0255

摘要： Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.

摘要翻译： 提供一种静电放电（ESD）保护装置及其制造方法。 在一个示例中，ESD保护装置包括形成在衬底中的齐纳二极管区域和邻近齐纳二极管区域形成的N型金属氧化物半导体（NMOS）器件。 齐纳二极管区域具有两个掺杂区域，位于两个掺杂区域之间的接地电位的栅极和在衬底中形成的两个光掺杂漏极（LDD）特征。 LDD特征之一位于两个掺杂区域和栅极之间。 NMOS器件包括形成在衬底中的源极和漏极，以及位于源极和漏极之间的第二栅极。

公开(公告)号：US20130038418A1

公开(公告)日：2013-02-14

申请号：US13206584

申请日：2011-08-10

申请人： Ping-Lin Yang ,  Jun-De Jin ,  Fu-Lung Hsueh ,  Sa-Lly Liu ,  Tong-Chern Ong ,  Chun-Jung Lin ,  Ya-Chen Kao

发明人： Ping-Lin Yang ,  Jun-De Jin ,  Fu-Lung Hsueh ,  Sa-Lly Liu ,  Tong-Chern Ong ,  Chun-Jung Lin ,  Ya-Chen Kao

IPC分类号： H01F38/14 ,  H01F41/00

CPC分类号： H01L25/0657 ,  H01F5/00 ,  H01F27/2804 ,  H01F41/046 ,  H01F2027/2809 ,  H01L23/48 ,  H01L23/5227 ,  H01L2225/06531 ,  H01L2924/0002 ,  Y10T29/4902 ,  H01L2924/00

摘要： A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.

摘要翻译： 通信结构包括具有第一线圈的第一半导体衬底和在第一半导体衬底上方具有第二线圈的第二半导体衬底。 第一和第二线圈的内边缘限定在第一线圈下方延伸并在第二线圈之上的体积的边界。 铁磁芯至少部分地位于边界内，使得在第一和第二线圈之间提供互感以在第一和第二线圈之间无线地传输信号或电力。

公开(公告)号：US07968967B2

公开(公告)日：2011-06-28

申请号：US11487849

申请日：2006-07-17

申请人： Ming-Tsong Wang ,  Tong-Chern Ong

发明人： Ming-Tsong Wang ,  Tong-Chern Ong

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a semiconductor substrate, a power source, and a stacked structure over the semiconductor substrate and coupled to the power source. The stacked structure includes a bottom electrode, a top electrode, and an insulation layer between the top electrode and the bottom electrode, wherein the insulation layer has a breakdown voltage lower than a pre-determined write voltage provided by the power source and higher than a pre-determined read voltage provided by the power source.

摘要翻译： 半导体结构包括在半导体衬底上的半导体衬底，电源和层叠结构，并且耦合到电源。 堆叠结构包括底部电极，顶部电极和顶部电极和底部电极之间的绝缘层，其中绝缘层具有低于由电源提供的预定写入电压的击穿电压，并且高于 由电源提供的预定读取电压。

公开(公告)号：US6124168A

公开(公告)日：2000-09-26

申请号：US337131

申请日：1994-11-10

申请人： Tong-Chern Ong

发明人： Tong-Chern Ong

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7881 ,  H01L27/115

摘要： A method of making an electrically erasable non-volatile EPROM memory device and the device itself having an asymmetric floating gate with respect to a buried source region and a buried drain region is disclosed. A patterned floating gate member is formed over a portion of the source region and a portion of the drain region producing a floating gate-to-source overlap and a floating gate-to-drain overlap, respectively, such that the floating gate-to-source overlap is less than the floating gate-to-drain overlap.

摘要翻译： 公开了一种制造电可擦除非易失性EPROM存储器件的方法，并且该器件本身具有相对于掩埋源极区和埋漏区的非对称浮置栅。 在源极区域的一部分上形成图案化的浮置栅极部件，漏极区域的一部分分别产生浮置栅极至源极重叠和浮置栅极至漏极重叠，使得浮动栅极 - 源重叠小于浮置栅极至漏极重叠。

公开(公告)号：US5548549A

公开(公告)日：1996-08-20

申请号：US399777

申请日：1995-03-07

申请人： Tong-Chern Ong

发明人： Tong-Chern Ong

IPC分类号： G11C5/14 ,  G11C11/56 ,  G11C16/30 ,  G11C11/34

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C16/30 ,  G11C5/147

摘要： A method and device to compensate for the series resistance effect along, for example, the source region in an electrically programmable read only memory array is described. One or more resistors are provided between the ground contact and ground. When a cell is programmed, the source is coupled to ground through one or more of the resistors, such that the resistance between source and ground for all cells is approximately equal. Therefore, the potential of the source of each cell is approximately equal for all cells during programming. In this way, the potential difference between the control gate and source is approximately equal for every cell, thereby resulting in more uniform programming levels and therefore more uniform threshold voltages. The method and device of the present invention is particularly applicable to multi-level cells, which employ several different threshold voltages to represent several different logic states. In addition to providing for uniform threshold voltages, the resistors of the present invention can be used to provide for programming to different levels using a single programming voltage on the control gate. For each level, the source of a cell is coupled to ground through one or more resistors, such that the potential difference between the control gate and the source has the appropriate value for that level.

公开(公告)号：US20100001335A1

公开(公告)日：2010-01-07

申请号：US12168545

申请日：2008-07-07

申请人： Ming-Tsong Wang ,  Tong-Chern Ong ,  Albert Chin ,  Hsueh-Jen Yang

发明人： Ming-Tsong Wang ,  Tong-Chern Ong ,  Albert Chin ,  Hsueh-Jen Yang

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L29/513 ,  H01L29/518

摘要： A semiconductor device includes a semiconductor substrate; a tunneling layer over the semiconductor substrate, wherein the tunneling layer has a first conduction band; a storage layer over the tunneling layer, wherein the storage layer has a second conduction band; a blocking layer over the storage layer, wherein the blocking layer has a third conduction band; a gate electrode over the blocking layer; and at least one of a first leakage-inhibition layer and a second leakage-inhibition layer. The first leakage-inhibition layer is between the tunneling layer and the storage layer, and has a fourth conduction band lower than the first conduction band. The second leakage-inhibition layer is between the blocking layer and the gate electrode, and has a fifth conduction band lower than the third conduction band.

摘要翻译： 半导体器件包括半导体衬底; 在所述半导体衬底上的隧道层，其中所述隧道层具有第一导带; 在所述隧道层上的存储层，其中所述存储层具有第二导带; 在所述存储层上的阻挡层，其中所述阻挡层具有第三导带; 阻挡层上的栅电极; 以及第一泄漏抑制层和第二泄漏抑制层中的至少一个。 第一泄漏抑制层在隧道层和存储层之间，并且具有比第一导带低的第四导带。 第二泄漏抑制层位于阻挡层和栅电极之间，并且具有比第三导带低的第五导带。

公开(公告)号：US20070272916A1

公开(公告)日：2007-11-29

申请号：US11440667

申请日：2006-05-25

申请人： Ming-Tsong Wang ,  Tong-Chern Ong ,  Albert Chin ,  Chun-Hung Lai

发明人： Ming-Tsong Wang ,  Tong-Chern Ong ,  Albert Chin ,  Chun-Hung Lai

IPC分类号： H01L29/06

CPC分类号： H01L29/792 ,  H01L29/517 ,  H01L29/66833

摘要： A flash memory cell includes a substrate and a gate structure formed on the substrate. The gate structure includes a tunneling layer over the substrate, a storage layer over the tunneling layer, a blocking layer over the storage layer, and a gate electrode over the dielectric. The storage layer preferably has a conduction band lower than a conduction band of silicon. The blocking layer is preferably formed of a high-k dielectric material.

摘要翻译： 闪存单元包括形成在基板上的基板和栅极结构。 栅极结构包括在衬底上的隧道层，隧道层上的存储层，存储层上的阻挡层和电介质上的栅电极。 存储层优选具有比硅的导带低的导带。 阻挡层优选由高k电介质材料形成。

公开(公告)号：US5233562A

公开(公告)日：1993-08-03

申请号：US815945

申请日：1991-12-30

申请人： Tong-Chern Ong ,  Ho-Chun Liou ,  Gregory E. Atwood

发明人： Tong-Chern Ong ,  Ho-Chun Liou ,  Gregory E. Atwood

IPC分类号： G11C16/14 ,  G11C16/34 ,  G11C29/02 ,  G11C29/50

CPC分类号： G11C16/3409 ,  G11C16/14 ,  G11C16/3404 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50 ,  G11C29/50004 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5006

摘要： A method of reprogramming field-effect memory cells of a memory array of an electrically erasable flash memory device is described. Each cell has a drain, a source, and a control gate. The drains of the cells are electrically connected to a bit line of the memory array. The cells are programmed and erased. The cells are repaired by grounding the sources and the control gates and taking the bit line to a predetermined potential. The memory array is selectively programmed. Other embodiments include repairing field-effect memory cells connected to a source line or part of a word line. Verification may be done between the repair step and selectively programming step.

摘要翻译： 描述了重新编程电可擦除闪存器件的存储器阵列的场效应存储器单元的方法。 每个单元都有漏极，源极和控制栅极。 电池的漏极电连接到存储器阵列的位线。 单元被编程和擦除。 通过使源极和控制栅极接地并将位线置于预定电位来修复电池。 存储器阵列被有选择地编程。 其他实施例包括修复连接到源线或字线的一部分的场效应存储器单元。 可以在修复步骤和选择性编程步骤之间进行验证。

公开(公告)号：US5196361A

公开(公告)日：1993-03-23

申请号：US700512

申请日：1991-05-15

申请人： Tong-Chern Ong ,  Been-Jon Woo

发明人： Tong-Chern Ong ,  Been-Jon Woo

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L29/7885 ,  H01L27/115

摘要： A method for making a device and the device itself which utilizes selectively doping part of the channel directly adjacent to the source to improve source-channel junction breakdown voltage is disclosed. This is accomplished through reduced dopant incorporation in the channel directly adjacent to the source during the channel doping steps. The portion of the channel which receives less channel dopant should not be so great that the charging of the floating gate is significantly altered.

摘要翻译： 公开了一种制造器件和器件本身的方法，其利用选择性地掺杂与源极相邻的沟道的一部分来改善源极结击穿电压。 这通过在沟道掺杂步骤期间通过与源极直接相邻的沟道中的掺杂剂掺杂减少来实现。 接收较少通道掺杂剂的通道的部分不应该太大，使得浮动栅极的充电被显着改变。