公开(公告)号：US20050040470A1

公开(公告)日：2005-02-24

申请号：US10951377

申请日：2004-09-28

申请人： Shu-Ya Chuang ,  Jing-Horng Gau ,  Anchor Chen

发明人： Shu-Ya Chuang ,  Jing-Horng Gau ,  Anchor Chen

IPC分类号： H01L21/331 ,  H01L21/00 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66242 ,  H01L29/66318

摘要： A method for fabricating a self-aligned bipolar transistor, wherein a substrate having an epitaxial layer formed thereon as a base is provided. After this, a first dielectric layer, a second dielectric layer are sequentially formed on the epitaxial layer, followed by forming an opening in the second dielectric layer. A conductive spacer is formed on the sidewall of the opening. Using the second dielectric layer and the conductive spacer as a mask, a first dielectric layer in the opening is removed. A conductive layer is then formed in the opening as an emitter, followed by completely removing the second dielectric layer. A doping is conducted on the emitter. Using the emitter and the conductive spacer as a mask, a part of the first dielectric layer is removed. Further using the emitter and the conductive spacer as a mask, another doping is conducted to form a part of the epitaxial layer as a base contact region.

摘要翻译： 一种用于制造自对准双极晶体管的方法，其中提供了其上形成有外延层作为基底的基板。 之后，在外延层上依次形成第一电介质层，第二电介质层，随后在第二电介质层中形成开口。 在开口的侧壁上形成导电间隔物。 使用第二电介质层和导电间隔物作为掩模，去除开口中的第一介电层。 然后在开口中形成导电层作为发射极，然后完全去除第二电介质层。 在发射极上进行掺杂。 使用发射极和导电间隔物作为掩模，去除第一介电层的一部分。 进一步使用发射极和导电间隔物作为掩模，进行另一掺杂以形成作为基极接触区域的外延层的一部分。

公开(公告)号：US06884689B2

公开(公告)日：2005-04-26

申请号：US10290635

申请日：2002-11-12

申请人： Shu-Ya Chuang ,  Jing-Horng Gau ,  Anchor Chen

发明人： Shu-Ya Chuang ,  Jing-Horng Gau ,  Anchor Chen

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/66318

摘要： A method for fabricating a self-aligned bipolar transistor, wherein a substrate having an epitaxial layer formed thereon as a base is provided. After this, a first dielectric layer, a second dielectric layer are sequentially formed on the epitaxial layer, followed by forming an opening in the second dielectric layer. A conductive spacer is formed on the sidewall of the opening. Using the second dielectric layer and the conductive spacer as a mask, a first dielectric layer in the opening is removed. A conductive layer is then formed in the opening as an emitter, followed by completely removing the second dielectric layer. A doping is conducted on the emitter. Using the emitter and the conductive spacer as a mask, a part of the first dielectric layer is removed. Further using the emitter and the conductive spacer as a mask, another doping is conducted to form a part of the epitaxial layer as a base contact region.

公开(公告)号：US20050017322A1

公开(公告)日：2005-01-27

申请号：US10921457

申请日：2004-08-18

申请人： Jing-Horng Gau ,  Anchor Chen

发明人： Jing-Horng Gau ,  Anchor Chen

IPC分类号： H01L27/08 ,  H01L29/00 ,  H01L21/00

CPC分类号： H01L27/0808

摘要： A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.

摘要翻译： 一种可变电容器，包括具有第一类型离子掺杂掩埋层，第一类型离子掺杂阱，第二类型离子掺杂区和其上的导电层的衬底。 在衬底内形成第一种类型的离子掺杂阱。 第一种类型的离子掺杂阱具有空腔。 第一类离子掺杂掩埋层位于第一类离子掺杂阱下的衬底中。 连接第一种离子掺杂掩埋层和第一种离子掺杂阱。 第二类离子掺杂区位于第一类型离子掺杂阱的空腔的底部。 导电层位于第一类型的离子掺杂掩埋层之上并与之连接。

公开(公告)号：US06882029B1

公开(公告)日：2005-04-19

申请号：US10707221

申请日：2003-11-27

申请人： Jing-Horng Gau ,  Anchor Chen

发明人： Jing-Horng Gau ,  Anchor Chen

IPC分类号： H01L27/08 ,  H01L29/93 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/0811 ,  H01L27/0808 ,  H01L29/93

摘要： A PN-junction varactor includes a first ion well of first conductivity type formed on a semiconductor substrate of second conductivity type. A first dummy gate is formed over the first ion well. A first gate dielectric layer is formed between the first dummy gate and the first ion well. A second dummy gate is formed over the first ion well at one side of the first dummy gate. A second gate dielectric layer is formed between the second dummy gate and the first ion well. A first heavily doped region of the second conductivity type is located in the first ion well between the first dummy gate and the second dummy gate. The first heavily doped region of the second conductivity type serving as an anode of the PN-junction varactor. Second heavily doped regions of the first conductivity type located in the first ion well at one side of the first dummy gate that is opposite to the first heavily doped region and at one side of the second dummy gate that is opposite to the first heavily doped region, the second heavily doped regions being electrically connected to each other and serving as a cathode of the PN junction varactor.

摘要翻译： PN结变容二极管包括形成在第二导电类型的半导体衬底上的第一导电类型的第一离子阱。 在第一离子阱上形成第一伪栅极。 在第一虚拟栅极和第一离子阱之间形成第一栅极介电层。 在第一虚拟栅极的一侧上的第一离子阱上形成第二伪栅极。 在第二虚拟栅极和第一离子阱之间形成第二栅极电介质层。 第二导电类型的第一重掺杂区域位于第一伪栅极和第二虚拟栅极之间的第一离子阱中。 第二导电类型的第一重掺杂区域用作PN结变容二极管的阳极。 第一导电类型的第二重掺杂区域位于第一伪栅极的与第一重掺杂区域相对的一侧处的第一离子阱中，并且位于与第一重掺杂区域相反的第二伪栅极的一侧 ，第二重掺杂区彼此电连接并用作PN结变容二极管的阴极。

公开(公告)号：US06190962B1

公开(公告)日：2001-02-20

申请号：US09467590

申请日：1999-12-20

申请人： Anchor Chen ,  Jing-Horng Gau

发明人： Anchor Chen ,  Jing-Horng Gau

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L27/10852 ,  H01L28/84

摘要： A fabrication method for a capacitor is proposed, beginning with a semiconductor substrate having a bit line and a planarized first dielectric layer formed thereon. A first silicon nitride layer is formed on the first dielectric layer, followed by forming in sequence a second dielectric layer and a second silicon nitride layer on the first silicon nitride layer. A photolithography and etching process is performed to form an opening in the second dielectric layer and the second silicon nitride layer. A conducting spacer is formed on a sidewall of the opening. With the spacer serving as a mask, the first silicon nitride layer and the first dielectric layer are etched to form a terminal contact opening. A conducting layer is then formed to cover the second silicon nitride layer and to fill the terminal contact opening, while the conducting layer on the second silicon nitride layer is removed by etching back. The second silicon nitride layer and the second dielectric layer are removed to expose a part of the conducting layer. A hemispherical grain layer is coated on the exposed surface of the conducting layer to complete manufacture of a lower electrode, while the lower electrode is covered by a dielectric film and an upper electrode to complete manufacture of the capacitor.

摘要翻译： 提出了一种用于电容器的制造方法，从形成有位线和平坦化的第一介电层的半导体衬底开始。 在第一介电层上形成第一氮化硅层，然后依次在第一氮化硅层上形成第二介电层和第二氮化硅层。 进行光刻和蚀刻工艺以在第二介电层和第二氮化硅层中形成开口。 导电间隔件形成在开口的侧壁上。 利用间隔物作为掩模，蚀刻第一氮化硅层和第一介电层以形成端子接触开口。 然后形成导电层以覆盖第二氮化硅层并填充端子接触开口，同时通过蚀刻去除第二氮化硅层上的导电层。 去除第二氮化硅层和第二介电层以暴露导电层的一部分。 半导体晶粒层涂覆在导电层的暴露表面上以完成下电极的制造，而下电极被电介质膜和上电极覆盖以完成电容器的制造。

公开(公告)号：US06905935B1

公开(公告)日：2005-06-14

申请号：US10707260

申请日：2003-12-02

申请人： Jing-Horng Gau ,  Anchor Chen

发明人： Jing-Horng Gau ,  Anchor Chen

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/7322

摘要： A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third doping region of the first conductivity type is formed in an upper portion of the second doping region. A shielding layer is formed and a portion of the shielding layer is removed to form an opening shielding layer to expose a portion of the third doping region. Subsequently, a doping layer of the second conductivity type is formed on a surface of the third doping region. A self-aligned silicidation process is performed to form a silicide layer on the surfaces of the second doping region, the third doping region and the doping layer, the silicide layer functioning as a contact region of a vertical bipolar junction transistor.

摘要翻译： 半导体晶片包括第一导电类型的第一掺杂区域，第二导电类型的第二掺杂区域和位于第一掺杂区域和第二掺杂区域的表面上的多个隔离结构。 第一导电类型的第三掺杂区形成在第二掺杂区的上部。 形成屏蔽层，并且去除屏蔽层的一部分以形成露出第三掺杂区域的一部分的开口屏蔽层。 随后，在第三掺杂区的表面上形成第二导电类型的掺杂层。 执行自对准硅化工艺以在第二掺杂区域，第三掺杂区域和掺杂层的表面上形成硅化物层，硅化物层用作垂直双极结型晶体管的接触区域。

公开(公告)号：US20050118772A1

公开(公告)日：2005-06-02

申请号：US10707260

申请日：2003-12-02

申请人： Jing-Horng Gau ,  Anchor Chen

发明人： Jing-Horng Gau ,  Anchor Chen

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/7322

摘要： A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third doping region of the first conductivity type is formed in an upper portion of the second doping region. A shielding layer is formed and a portion of the shielding layer is removed to form an opening shielding layer to expose a portion of the third doping region. Subsequently, a doping layer of the second conductivity type is formed on a surface of the third doping region. A self-aligned silicidation process is performed to form a silicide layer on the surfaces of the second doping region, the third doping region and the doping layer, the silicide layer functioning as a contact region of a vertical bipolar junction transistor.

摘要翻译： 半导体晶片包括第一导电类型的第一掺杂区域，第二导电类型的第二掺杂区域和位于第一掺杂区域和第二掺杂区域的表面上的多个隔离结构。 第一导电类型的第三掺杂区形成在第二掺杂区的上部。 形成屏蔽层，并且去除屏蔽层的一部分以形成露出第三掺杂区域的一部分的开口屏蔽层。 随后，在第三掺杂区的表面上形成第二导电类型的掺杂层。 执行自对准硅化工艺以在第二掺杂区域，第三掺杂区域和掺杂层的表面上形成硅化物层，硅化物层用作垂直双极结型晶体管的接触区域。

公开(公告)号：US07157766B2

公开(公告)日：2007-01-02

申请号：US10921457

申请日：2004-08-18

申请人： Jing-Horng Gau ,  Anchor Chen

发明人： Jing-Horng Gau ,  Anchor Chen

IPC分类号： H01L27/108

CPC分类号： H01L27/0808

摘要： A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.

摘要翻译： 一种可变电容器，包括具有第一类型离子掺杂掩埋层，第一类型离子掺杂阱，第二类型离子掺杂区和其上的导电层的衬底。 在衬底内形成第一种类型的离子掺杂阱。 第一种类型的离子掺杂阱具有空腔。 第一类离子掺杂掩埋层位于第一类离子掺杂阱下的衬底中。 连接第一种离子掺杂掩埋层和第一种离子掺杂阱。 第二类离子掺杂区位于第一类型离子掺杂阱的空腔的底部。 导电层位于第一类型的离子掺杂掩埋层之上并与之连接。

公开(公告)号：US6159789A

公开(公告)日：2000-12-12

申请号：US306093

申请日：1999-05-06

申请人： Shu-Ya Chuang ,  Anchor Chen

发明人： Shu-Ya Chuang ,  Anchor Chen

IPC分类号： H01L21/8242

CPC分类号： H01L27/10876 ,  H01L27/10852 ,  H01L27/10885

摘要： A method for fabricating a capacitor in DRAM. A horizontal buried doped region is formed in a substrate. A pad oxide layer and a mask layer are formed in sequence on the substrate. A plurality of first trenches is formed in the substrate. Thus, a plurality of bit lines is formed in the substrate. A plurality of second trenches is formed in the substrate to expose the surface of the bit lines, wherein the second trenches cross the first trenches. Thus, a plurality of silicon islands on the bit lines is formed. A first insulation layer is formed in the first trenches and the second trenches, wherein the sidewall of the silicon islands are partly exposed and doped regions are formed in the exposed sidewall. A gate oxide layer is formed on the sidewall of the silicon islands. A spacer is formed on the gate oxide layer. A second insulation layer is formed over the substrate. The mask layer and the pad oxide layer are removed to expose the top surfaces of the silicon islands. A patterned conductive layer is formed over the substrate. A dielectric layer and an upper electrode are formed in sequence over the substrate.

摘要翻译： 一种在DRAM中制造电容器的方法。 在衬底中形成水平掩埋掺杂区域。 在衬底上依次形成衬垫氧化物层和掩模层。 在基板中形成多个第一沟槽。 因此，在基板中形成多个位线。 在衬底中形成多个第二沟槽以暴露位线的表面，其中第二沟槽穿过第一沟槽。 因此，形成位线上的多个硅岛。 第一绝缘层形成在第一沟槽和第二沟槽中，其中硅岛的侧壁部分地暴露，并且在暴露的侧壁中形成掺杂区域。 在硅岛的侧壁上形成栅氧化层。 在栅极氧化层上形成间隔物。 在衬底上形成第二绝缘层。 去除掩模层和焊盘氧化物层以露出硅岛的顶表面。 在衬底上形成图案化的导电层。 电介质层和上电极依次形成在衬底上。

公开(公告)号：US07608473B2

公开(公告)日：2009-10-27

申请号：US11099058

申请日：2005-04-05

申请人： Anchor Chen

发明人： Anchor Chen

IPC分类号： H01L21/00

CPC分类号： H01L27/14625 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14643

摘要： An image sensor and a manufacturing method thereof are provided. The image sensor includes a plurality of sensors, an inter-layer dielectric layer formed over the sensors, a first inter-metal dielectric layer formed over the inter-layer dielectric layer, and a plurality of first via walls formed in the first inter-metal dielectric layer, wherein each of the first via walls is formed around each of the sensors. In addition, the image sensor further includes a second inter-metal dielectric layer formed over the first inter-metal dielectric layer and a plurality of second via walls formed in the second inter-metal dielectric layer, wherein each of the second via walls is formed around each of the sensors. Therefore, the light leakage between different pixels and the problem of crosstalk are solved, and the spatial resolution and the photo sensitivity of the image sensor are enhanced.

摘要翻译： 提供了图像传感器及其制造方法。 图像传感器包括多个传感器，形成在传感器上的层间电介质层，形成在层间电介质层之上的第一金属间介电层和形成在第一金属间的多个第一通孔 电介质层，其中每个所述第一通孔壁围绕每个所述传感器形成。 此外，图像传感器还包括形成在第一金属间介电层上的第二金属间介电层和形成在第二金属间介电层中的多个第二通孔，其中形成有第二通孔壁 围绕每个传感器。 因此，解决了不同像素之间的漏光和串扰问题，提高了图像传感器的空间分辨率和光敏度。