公开(公告)号：US06200854B1

公开(公告)日：2001-03-13

申请号：US09466685

申请日：1999-12-20

申请人： Shu-Ya Chuang

发明人： Shu-Ya Chuang

IPC分类号： H01L218242

CPC分类号： H01L27/10855 ,  H01L27/10814 ,  H01L27/10888

摘要： A method of fabricating dynamic random access memory. A conductive layer, a metal silicide layer, a first cap layer and a second cap layer are formed and patterned to form gate structures on the substrate. A first oxide layer is formed over the sidewalls of the metal silicide layer and the conductive layer as well as over the exposed substrate. First spacers are formed on the sidewalls of the gate structures. A second oxide layer is formed over the substrate. Second spacers are formed on the sidewalls of the second oxide layer. A third oxide layer is formed over the substrate. The second spacers, the second oxide layer and a portion of the first oxide layer are removed to expose a portion of the substrate. Contact pads that expose the second cap layer and a portion of the first spacers are formed, and then a first dielectric layer is formed over the entire substrate. Source/drain regions are formed on each side of the third oxide layer in the substrate. Bit lines that connect electrically with the contact pad through a contact in the first dielectric layer are formed. A second dielectric layer is formed over the entire substrate. A storage node electrode that connects electrically with the contact pad through a contact in the second dielectric layer is formed.

摘要翻译： 一种制造动态随机存取存储器的方法。 形成导电层，金属硅化物层，第一覆盖层和第二覆盖层并构图以在衬底上形成栅极结构。 第一氧化物层形成在金属硅化物层和导电层的侧壁上以及暴露的衬底之上。 第一间隔物形成在栅极结构的侧壁上。 在衬底上形成第二氧化物层。 在第二氧化物层的侧壁上形成第二间隔物。 在衬底上形成第三氧化物层。 去除第二间隔物，第二氧化物层和第一氧化物层的一部分以暴露衬底的一部分。 形成露出第二盖层和一部分第一间隔物的接触焊盘，然后在整个基板上形成第一介电层。 源极/漏极区域形成在衬底中的第三氧化物层的每一侧上。 形成通过第一电介质层中的触点与接触焊盘电连接的位线。 在整个基板上形成第二电介质层。 形成了通过第二电介质层中的触点与接触焊盘电连接的存储节点电极。

公开(公告)号：US6159808A

公开(公告)日：2000-12-12

申请号：US437952

申请日：1999-11-12

申请人： Shu-Ya Chuang

发明人： Shu-Ya Chuang

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10873 ,  H01L27/10814 ,  H01L27/10888

摘要： A method of forming a dynamic random access memory cell such that the gate conductive layer, the bit line contact, the node contact, the bit line and the node contact plug are all formed using self-aligned processes. By employing the self-aligned method of forming DRAM cell, isolation structures are no longer etched in the process of forming the node contact opening. In addition, the aspect ratio of the node contact opening is reduced and processing window is thereby widened.

摘要翻译： 形成动态随机存取存储单元的方法，使得栅极导电层，位线接触，节点接触，位线和节点接​​触插塞全部使用自对准工艺形成。 通过采用形成DRAM单元的自对准方法，在形成节点接触开口的过程中不再蚀刻隔离结构。 此外，节点接触开口的纵横比减小，从而加宽了窗口。

公开(公告)号：US06884689B2

公开(公告)日：2005-04-26

申请号：US10290635

申请日：2002-11-12

申请人： Shu-Ya Chuang ,  Jing-Horng Gau ,  Anchor Chen

发明人： Shu-Ya Chuang ,  Jing-Horng Gau ,  Anchor Chen

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/66318

摘要： A method for fabricating a self-aligned bipolar transistor, wherein a substrate having an epitaxial layer formed thereon as a base is provided. After this, a first dielectric layer, a second dielectric layer are sequentially formed on the epitaxial layer, followed by forming an opening in the second dielectric layer. A conductive spacer is formed on the sidewall of the opening. Using the second dielectric layer and the conductive spacer as a mask, a first dielectric layer in the opening is removed. A conductive layer is then formed in the opening as an emitter, followed by completely removing the second dielectric layer. A doping is conducted on the emitter. Using the emitter and the conductive spacer as a mask, a part of the first dielectric layer is removed. Further using the emitter and the conductive spacer as a mask, another doping is conducted to form a part of the epitaxial layer as a base contact region.

公开(公告)号：US06218241B1

公开(公告)日：2001-04-17

申请号：US09536595

申请日：2000-03-28

申请人： Shu-Ya Chuang

发明人： Shu-Ya Chuang

IPC分类号： H01L218242

CPC分类号： H01L27/10873 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10891

摘要： A fabrication method for a compact DRAM cell is described. The method includes forming a first doped polysilicon layer, a metal barrier layer, a second doped polysilicon layer, a metal silicide layer and a patterned silicon oxide layer on a semiconductor substrate. A first silicon nitride spacer is then formed on the sidewall of the patterned silicon oxide layer, followed by a removal of the patterned silicon oxide layer and parts of a metal silicide layer, the second doped polysilicon layer and the metal silicide layer to form an upper part of the gate. A second silicon nitride spacer is then formed on the sidewall of the upper part of the gate, followed by a removal of the exposed first doped polysilicon layer to form the lower part of the gate. A bit line contact and a node contact are subsequently formed on both side of the gate above the lower part of the gate.

摘要翻译： 描述了一种紧凑DRAM单元的制造方法。 该方法包括在半导体衬底上形成第一掺杂多晶硅层，金属势垒层，第二掺杂多晶硅层，金属硅化物层和图案氧化硅层。 然后在图案化氧化硅层的侧壁上形成第一氮化硅间隔物，随后去除图案化氧化硅层和部分金属硅化物层，第二掺杂多晶硅层和金属硅化物层以形成上部 部分门。 然后在栅极的上部的侧壁上形成第二氮化硅间隔物，随后去除暴露的第一掺杂多晶硅层以形成栅极的下部。 随后在门的下部的栅极的两侧上形成位线接触和节点接触。

公开(公告)号：US6083804A

公开(公告)日：2000-07-04

申请号：US103957

申请日：1998-06-24

申请人： Shu-Ya Chuang

发明人： Shu-Ya Chuang

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/20

CPC分类号： H01L28/84 ,  H01L28/91 ,  H01L21/3145 ,  H01L21/31604 ,  H01L28/55

摘要： The invention is a method for fabricating a capacitor in a dynamic random access memory. The capacitor has double cylinder structure and is fabricated by utilizing an insulating side wall spacer to pre-define the capacitor structure. Then, a wet etching process is applied to remove the insulating side wall spacer and expose a surface of a structured lower electrode. Then, a dielectric thin film and an upper electrode are formed over the surface of the lower electrode sequentially to form the capacitor.

摘要翻译： 本发明是一种在动态随机存取存储器中制造电容器的方法。 电容器具有双缸结构，并且通过利用绝缘侧壁间隔物预先限定电容器结构来制造。 然后，施加湿蚀刻工艺以除去绝缘侧壁间隔物并暴露结构化下电极的表面。 然后，依次在下电极的表面上形成电介质薄膜和上电极，形成电容器。

公开(公告)号：US06479307B2

公开(公告)日：2002-11-12

申请号：US09854007

申请日：2001-05-10

申请人： Shu-Ya Chuang ,  Gow-Wei Sun ,  Ga-Ming Hong ,  Steven Chen ,  Pei-Jen Wang

发明人： Shu-Ya Chuang ,  Gow-Wei Sun ,  Ga-Ming Hong ,  Steven Chen ,  Pei-Jen Wang

IPC分类号： H01L2166

CPC分类号： H01L22/34 ,  H01L21/76802

摘要： A method of monitoring loss of silicon nitride, used to monitor the loss of a first etch stop layer below a first insulating layer in a first contact opening opening after the first contact opening is formed in the first insulating layer over a device region and scribe line of a wafer. A dummy wafer is provided on which stacks in sequence a second etch stop layer and a second insulating layer. The second insulating layer is patterned by removing a portion of the second insulating layer, so that a monitoring opening that exposes the second etch stop layer and a second contact opening are formed in the second insulating layer. A first measuring step is performed to measure a first thickness loss and a second thickness loss from the second etch stop layer exposed respectively by the monitoring opening and the second contact opening on the dummy wafer. And a correlation is established from the first and second thickness losses. A second measuring step is performed to measure a third thickness loss from the first etch stop layer exposed by the monitoring opening on the wafer. The result is then compared with the correlation to deduce a fourth thickness loss from the first contact opening on the wafer.

摘要翻译： 一种监测氮化硅损失的方法，用于监测在第一接触开口之后的第一绝缘层中的第一绝缘层下方的第一蚀刻停止层的损失，该第一绝缘层在第一绝缘层上形成在器件区域和划线 的晶片。 提供了一个虚设晶片，其上依次叠置有第二蚀刻停止层和第二绝缘层。 通过去除第二绝缘层的一部分来图形化第二绝缘层，使得在第二绝缘层中形成暴露第二蚀刻停止层和第二接触开口的监视开口。 执行第一测量步骤以测量分别由伪晶片上的监视开口和第二接触开口暴露的第二蚀刻停止层的第一厚度损失和第二厚度损失。 并且从第一和第二厚度损失建立相关性。 执行第二测量步骤以测量由晶片上的监视开口暴露的第一蚀刻停止层的第三厚度损失。 然后将结果与相关性进行比较以推导出晶片上的第一接触开口的第四厚度损失。

公开(公告)号：US06172388B2

公开(公告)日：2001-01-09

申请号：US09270027

申请日：1999-03-16

申请人： Shu-Ya Chuang

发明人： Shu-Ya Chuang

IPC分类号： H01L27108

CPC分类号： H01L27/108 ,  H01L27/10808

摘要： An improved method for fabricating DRAM with a thin film transistor can increase reading and writing speed. In this method, a substrate with a transfer transistor, a word line, a bit line and an interlayer dielectric layer is provided. A bit line contact and a terminal contact are formed in the interlayer dielectric layer. The bit line contact couples to the bit line and the terminal contact couples to the transfer transistor. The terminal contact is a T-shaped structure. An oxide layer is formed to cover the interlayer dielectric layer and the terminal contact to expose the bit line contact. A polysilicon layer is formed to cover the oxide layer and the bit line contact. An ion implantation step is performed to form a first doped region and a second doped region in the polysilicon layer. The polysilicon layer is patterned to make the first doped region into a source region and to make the second doped region into a drain region. The drain region is on one side of the terminal contact corresponding to the source region.

摘要翻译： 用薄膜晶体管制造DRAM的改进方法可以提高读写速度。 在该方法中，提供具有转移晶体管，字线，位线和层间电介质层的衬底。 在层间电介质层中形成位线接触和端子接触。 位线接触耦合到位线，并且端子触点耦合到转移晶体管。 端子触点是T形结构。 形成氧化物层以覆盖层间电介质层和端子触点以暴露位线接触。 形成多晶硅层以覆盖氧化物层和位线接触。 执行离子注入步骤以在多晶硅层中形成第一掺杂区域和第二掺杂区域。 图案化多晶硅层以使第一掺杂区域成为源极区域并使第二掺杂区域成为漏极区域。 漏极区域位于与源极区域对应的端子触点的一侧。

公开(公告)号：US6159789A

公开(公告)日：2000-12-12

申请号：US306093

申请日：1999-05-06

申请人： Shu-Ya Chuang ,  Anchor Chen

发明人： Shu-Ya Chuang ,  Anchor Chen

IPC分类号： H01L21/8242

CPC分类号： H01L27/10876 ,  H01L27/10852 ,  H01L27/10885

摘要： A method for fabricating a capacitor in DRAM. A horizontal buried doped region is formed in a substrate. A pad oxide layer and a mask layer are formed in sequence on the substrate. A plurality of first trenches is formed in the substrate. Thus, a plurality of bit lines is formed in the substrate. A plurality of second trenches is formed in the substrate to expose the surface of the bit lines, wherein the second trenches cross the first trenches. Thus, a plurality of silicon islands on the bit lines is formed. A first insulation layer is formed in the first trenches and the second trenches, wherein the sidewall of the silicon islands are partly exposed and doped regions are formed in the exposed sidewall. A gate oxide layer is formed on the sidewall of the silicon islands. A spacer is formed on the gate oxide layer. A second insulation layer is formed over the substrate. The mask layer and the pad oxide layer are removed to expose the top surfaces of the silicon islands. A patterned conductive layer is formed over the substrate. A dielectric layer and an upper electrode are formed in sequence over the substrate.

摘要翻译： 一种在DRAM中制造电容器的方法。 在衬底中形成水平掩埋掺杂区域。 在衬底上依次形成衬垫氧化物层和掩模层。 在基板中形成多个第一沟槽。 因此，在基板中形成多个位线。 在衬底中形成多个第二沟槽以暴露位线的表面，其中第二沟槽穿过第一沟槽。 因此，形成位线上的多个硅岛。 第一绝缘层形成在第一沟槽和第二沟槽中，其中硅岛的侧壁部分地暴露，并且在暴露的侧壁中形成掺杂区域。 在硅岛的侧壁上形成栅氧化层。 在栅极氧化层上形成间隔物。 在衬底上形成第二绝缘层。 去除掩模层和焊盘氧化物层以露出硅岛的顶表面。 在衬底上形成图案化的导电层。 电介质层和上电极依次形成在衬底上。

公开(公告)号：US5960282A

公开(公告)日：1999-09-28

申请号：US206065

申请日：1998-12-04

申请人： Shu-Ya Chuang

发明人： Shu-Ya Chuang

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823

摘要： A method for fabricating a DRAM cell with a vertical pass transistor is provided. The method of the invention includes sequentially forming a drain region, a gate structure, a source region, and a capacitor on a semiconductor substrate in a vertical distribution so that an area used by the drain region is the total area used by the DRAM cell on the substrate. In other world, the gate structure, the source region, and the capacitor are formed above the semiconductor substrate without direct contact.

摘要翻译： 提供了一种用垂直传输晶体管制造DRAM单元的方法。 本发明的方法包括在垂直分布中在半导体衬底上依次形成漏极区，栅极结构，源区和电容，使得漏极区所用的区域是由DRAM单元使用的总面积 底物。 在另一方面，栅极结构，源极区和电容器形成在半导体衬底的上方，而不会直接接触。

公开(公告)号：US20050040470A1

公开(公告)日：2005-02-24

申请号：US10951377

申请日：2004-09-28

申请人： Shu-Ya Chuang ,  Jing-Horng Gau ,  Anchor Chen

发明人： Shu-Ya Chuang ,  Jing-Horng Gau ,  Anchor Chen

IPC分类号： H01L21/331 ,  H01L21/00 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66242 ,  H01L29/66318

摘要： A method for fabricating a self-aligned bipolar transistor, wherein a substrate having an epitaxial layer formed thereon as a base is provided. After this, a first dielectric layer, a second dielectric layer are sequentially formed on the epitaxial layer, followed by forming an opening in the second dielectric layer. A conductive spacer is formed on the sidewall of the opening. Using the second dielectric layer and the conductive spacer as a mask, a first dielectric layer in the opening is removed. A conductive layer is then formed in the opening as an emitter, followed by completely removing the second dielectric layer. A doping is conducted on the emitter. Using the emitter and the conductive spacer as a mask, a part of the first dielectric layer is removed. Further using the emitter and the conductive spacer as a mask, another doping is conducted to form a part of the epitaxial layer as a base contact region.

摘要翻译： 一种用于制造自对准双极晶体管的方法，其中提供了其上形成有外延层作为基底的基板。 之后，在外延层上依次形成第一电介质层，第二电介质层，随后在第二电介质层中形成开口。 在开口的侧壁上形成导电间隔物。 使用第二电介质层和导电间隔物作为掩模，去除开口中的第一介电层。 然后在开口中形成导电层作为发射极，然后完全去除第二电介质层。 在发射极上进行掺杂。 使用发射极和导电间隔物作为掩模，去除第一介电层的一部分。 进一步使用发射极和导电间隔物作为掩模，进行另一掺杂以形成作为基极接触区域的外延层的一部分。