公开(公告)号：US09435841B2

公开(公告)日：2016-09-06

申请号：US13446394

申请日：2012-04-13

申请人： Shunhua Chang ,  James Paul Di Sarro ,  Robert J. Gauthier, Jr. ,  Nathan Jack ,  Souvick Mitra

发明人： Shunhua Chang ,  James Paul Di Sarro ,  Robert J. Gauthier, Jr. ,  Nathan Jack ,  Souvick Mitra

IPC分类号： H02H9/00 ,  G01R31/00 ,  H02H9/04 ,  G01R31/28 ,  H01L27/02 ,  H05K9/00

CPC分类号： G01R31/002 ,  G01R31/2851 ,  H01L27/0248 ,  H02H9/046 ,  H05K9/0067

摘要： A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.

摘要翻译： 提供了使用ESD测试系统在静电放电（ESD）测试期间保护集成电路内的器件的方法。 该方法包括将直流（DC）偏置电压施加到集成电路的至少一个器件的输入，并将ESD仿真信号施加到集成电路的至少一个其他输入。 施加的ESD模拟信号沿着第一电流路径传导到第一地，而与至少一个装置相关联的低电流信号沿着第二电流路径传导到第二地。 响应于由所施加的ESD模拟信号产生的第二接地上的信号变化，DC偏置电压在至少一个器件的输入和第二接地之间以基本恒定的值保持。

公开(公告)号：US08891212B2

公开(公告)日：2014-11-18

申请号：US13079946

申请日：2011-04-05

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H02H9/04 ,  H03K19/003 ,  H01L27/02

CPC分类号： H02H9/046 ,  H01L27/0262 ,  H03K19/00361 ,  Y10T29/49002

摘要： RC-trigger circuits for a semiconductor controlled rectifier (SCR), methods of providing electrostatic discharge (ESD) protection, and design structures for a RC-trigger circuit. The RC-trigger circuit is coupled to an input/output (I/O) signal pad by an isolation diode and is coupled to a power supply voltage by a power supply diode. Under normal operating conditions, the isolation diode is reverse biased, isolating the RC-trigger circuit from the input/output (I/O) pad, and the power supply diode is forward biased so that the RC-trigger circuit is supplied with power. The isolation diode may become forward biased during ESD events while the chip is unpowered, causing the RC-trigger circuit to trigger an SCR configured protect the signal pad from ESD into a conductive state. The power supply diode may become reverse biased during the ESD event, which isolates the power supply rail from the ESD voltage pulse.

摘要翻译： 用于半导体可控整流器（SCR）的RC触发电路，提供静电放电（ESD）保护的方法以及用于RC触发电路的设计结构。 RC触发电路通过隔离二极管耦合到输入/输出（I / O）信号焊盘，并通过电源二极管耦合到电源电压。 在正常工作条件下，隔离二极管反向偏置，将RC触发电路与输入/输出（I / O）焊盘隔离，电源二极管正向偏置，使RC触发电路供电。 在ESD事件期间，隔离二极管可能会在芯片未上电时产生正向偏置，导致RC触发电路触发SCR配置，从而将信号焊盘从ESD保护到导通状态。 在ESD事件期间，电源二极管可能会反向偏置，从而将电源轨与ESD电压脉冲隔离。

公开(公告)号：US08634174B2

公开(公告)日：2014-01-21

申请号：US13115492

申请日：2011-05-25

申请人： Michel J. Abou-Khalil ,  James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Yang Yang

发明人： Michel J. Abou-Khalil ,  James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Yang Yang

IPC分类号： H02H9/00 ,  H02H3/22

CPC分类号： H02H9/046 ,  G06F17/5063 ,  H01L27/0285

摘要： Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.

摘要翻译： 用于将场效应晶体管的栅极和栅极电介质与静电放电（ESD）隔离的保护电路，设计结构和方法。 保护场效应晶体管位于受保护的场效应晶体管和电压轨之间。 在正常工作条件下，保护场效应晶体管饱和，使受保护的场效应晶体管耦合到电压轨。 保护场效应晶体管可以在芯片无电源时响应于ESD事件而被驱动成截止状态，这增加了受保护的场效应晶体管的栅极与电压轨之间的ESD电流路径的串联电阻。 保护场效应晶体管两端的电压降可以降低受保护的场效应晶体管的栅极电介质上的ESD应力。 或者，现有的场效应晶体管的栅极和源极被选择性地耦合到提供ESD隔离到受保护的场效应晶体管。

公开(公告)号：US08138546B2

公开(公告)日：2012-03-20

申请号：US12127946

申请日：2008-05-28

申请人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

发明人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/7436 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

摘要： A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

摘要翻译： 包括硅控制整流器的集成电路的硅控制整流器和静电放电保护装置。 硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。

公开(公告)号：US07786535B2

公开(公告)日：2010-08-31

申请号：US12059034

申请日：2008-03-31

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

IPC分类号： H01L29/78

CPC分类号： H01L27/1203

摘要： Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first and second gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the first and second gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrently with a process forming other device isolation regions.

摘要翻译： 高压集成电路的设计结构。 使用绝缘体上半导体（SOI）衬底形成的设计结构可以包括具有位于第一和第二栅电极之间的半导体本体的器件结构。 第一和第二栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。 电介质层将第一和第二栅极电极与半导体本体分开。 这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，介电材料可与形成其它器件隔离区的工艺同时进行。

公开(公告)号：US07298008B2

公开(公告)日：2007-11-20

申请号：US11275638

申请日：2006-01-20

申请人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

发明人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/7436 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

摘要： Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

摘要翻译： 公开了一种硅控制整流器，制造硅控制整流器的方法和使用硅控整流器作为集成电路的静电放电保护器件。 硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。

公开(公告)号：US08686508B2

公开(公告)日：2014-04-01

申请号：US12553523

申请日：2009-09-03

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Robert Robison

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Robert Robison

IPC分类号： H01L23/62

CPC分类号： H01L21/324 ,  H01L27/0255 ,  H01L29/8611 ,  H01L29/866

摘要： Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

摘要翻译： 为纳秒电脉冲退火工艺提供了结构和方法。 形成静电放电（ESD）N + / P +结构的方法包括在衬底上形成N +扩散，并在衬底上形成P +扩散。 P +扩散与N +扩散电接触。 该方法还包括在N +扩散和P +扩散之间形成器件。 退火结构或材料的方法包括跨多个纳秒的静电放电（ESD）N + / P +结构施加电脉冲。

公开(公告)号：US08390068B2

公开(公告)日：2013-03-05

申请号：US13361051

申请日：2012-01-30

申请人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

发明人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

IPC分类号： H01L27/01 ,  H01L29/74 ,  H01L23/62

CPC分类号： H01L29/7436 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

摘要： A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

摘要翻译： 包括硅控制整流器的集成电路的硅控制整流器和静电放电保护装置。 硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。

公开(公告)号：US07518845B2

公开(公告)日：2009-04-14

申请号：US11422608

申请日：2006-06-07

申请人： Robert J. Gauthier, Jr. ,  Dimitrios K. Kontos ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Robert J. Gauthier, Jr. ,  Dimitrios K. Kontos ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H02H9/00 ,  H02H1/00

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) power clamp circuit including a RC-delay element coupled to a plurality of serialized inverter elements with a power clamp element and an ESD-triggered keeper device coupled to the plurality of inverters. During negative mode ESD events, the ESD-triggered keeper device is activated and assists the power clamp element to pull up and strongly conduct current to protect the circuit. Additionally, a method of ESD protection in a circuit is provided. The method includes coupling a RC-delay element to an input of a plurality of serialized inverter elements, coupling an output of the plurality of serialized inverters with an ESD-triggered keeper device and a power clamp element, triggering the ESD-triggered keeper device to turn on during negative ESD events and conducting current by the power clamp element with assistance of the ESD-triggered keeper device to protect the circuit as a result of negative ESD events.

摘要翻译： 一种静电放电（ESD）功率钳位电路，其包括耦合到多个串联反相器元件的RC延迟元件，其具有耦合到所述多个逆变器的功率钳位元件和ESD触发的保持器装置。 在负模式ESD事件期间，ESD触发的保护装置被激活，并且帮助电源钳位元件上拉并强烈地传导电流以保护电路。 另外，提供了电路中ESD保护的方法。 该方法包括将RC延迟元件耦合到多个串联反相器元件的输入端，将多个串联反相器的输出与ESD触发的保持器装置和功率钳位元件耦合，将ESD触发的保持器装置触发 在ESD ESD事件期间接通电源，并通过ESD触发的保护装置的辅助，通过电源钳位元件传导电流，以保护电路由于负ESD事件。

公开(公告)号：US08737028B2

公开(公告)日：2014-05-27

申请号：US13312047

申请日：2011-12-06

申请人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra

发明人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra

IPC分类号： H02H9/04 ,  G06F17/50

CPC分类号： H02H9/046

摘要： Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.

摘要翻译： 用于响应电压轨上的静电放电（ESD）事件，ESD保护电路以及ESD保护电路的设计结构的方法。 ESD保护电路的RC网络包括耦合到节点处的场效应晶体管的电容器。 RC网络的节点与逆变器的输入端相连。 场效应晶体管与反相器的输出端相连。 响应于ESD事件，触发信号从RC网络提供给逆变器的输入，该驱动器驱动钳位装置以从ESD电压放电来自电压轨。 响应于ESD事件，RC网络的RC时间常数增加以维持钳位装置的电流放电。