公开(公告)号：US20120241739A1

公开(公告)日：2012-09-27

申请号：US13428008

申请日：2012-03-23

申请人： Shunpei Yamazaki ,  Hiromichi Godo ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Hiromichi Godo ,  Yasuhiko Takemura

IPC分类号： H01L29/78

CPC分类号： H01L29/7869 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10826 ,  H01L27/10852 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/90 ,  H01L29/41733 ,  H01L29/785 ,  H01L29/78609

摘要： Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface and has a thickness of greater than or equal to 1 nm and less than or equal to 30 nm, a gate insulating film formed to cover the oxide semiconductor, and a strip-like gate which is formed to cover the gate insulating film and has a width of greater than or equal to 10 nm and less than or equal to 100 nm. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate, so that electrons injected from a source or a drain can be effectively removed, and most of the space between the source and the drain can be a depletion region; thus, off-state current can be reduced.

摘要翻译： 提供了一种具有小截止电流的场效应晶体管（FET），其用于小型化的半导体集成电路中。 场效应晶体管包括形成为基本上垂直于绝缘表面并且具有大于或等于1nm且小于或等于30nm的厚度的薄氧化物半导体，形成为覆盖氧化物半导体的栅极绝缘膜 以及形成为覆盖栅极绝缘膜并且具有大于或等于10nm且小于或等于100nm的宽度的条状栅极。 在这种结构中，薄氧化物半导体的三个表面被栅极覆盖，使得可以有效地去除从源极或漏极注入的电子，并且源极和漏极之间的大部分空间可以是耗尽区; 因此，可以减小截止电流。

公开(公告)号：US08754409B2

公开(公告)日：2014-06-17

申请号：US13428008

申请日：2012-03-23

申请人： Shunpei Yamazaki ,  Hiromichi Godo ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Hiromichi Godo ,  Yasuhiko Takemura

IPC分类号： H01L29/12

CPC分类号： H01L29/7869 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10826 ,  H01L27/10852 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/90 ,  H01L29/41733 ,  H01L29/785 ,  H01L29/78609

摘要： Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface and has a thickness of greater than or equal to 1 nm and less than or equal to 30 nm, a gate insulating film formed to cover the oxide semiconductor, and a strip-like gate which is formed to cover the gate insulating film and has a width of greater than or equal to 10 nm and less than or equal to 100 nm. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate, so that electrons injected from a source or a drain can be effectively removed, and most of the space between the source and the drain can be a depletion region; thus, off-state current can be reduced.

摘要翻译： 提供了一种具有小截止电流的场效应晶体管（FET），其用于小型化的半导体集成电路中。 场效应晶体管包括形成为基本上垂直于绝缘表面并且具有大于或等于1nm且小于或等于30nm的厚度的薄氧化物半导体，形成为覆盖氧化物半导体的栅极绝缘膜 以及形成为覆盖栅极绝缘膜并且具有大于或等于10nm且小于或等于100nm的宽度的条状栅极。 在这种结构中，薄氧化物半导体的三个表面被栅极覆盖，使得可以有效地去除从源极或漏极注入的电子，并且源极和漏极之间的大部分空间可以是耗尽区; 因此，可以减小截止电流。

公开(公告)号：US08957462B2

公开(公告)日：2015-02-17

申请号：US13314326

申请日：2011-12-08

申请人： Shunpei Yamazaki ,  Hiromichi Godo ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Hiromichi Godo ,  Yasuhiko Takemura

IPC分类号： H01L29/76 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/1083 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device such as a transistor with an excellent OFF characteristic even when a channel is short is provided. A periphery of a source is surrounded by an extension region and a halo region, a periphery of a drain is surrounded by an extension region and a halo region, and a substrate with low impurity concentration is not in contact with the source or the drain. Moreover, a high-work-function electrode is provided via a gate insulator, and electrons entering the vicinity of a surface of the substrate from the extension regions are eliminated. With such a structure, the impurity concentration of the channel region can be decreased even when the channel is short, and a favorable transistor characteristic can be obtained.

摘要翻译： 提供即使在通道短时也具有优异的OFF特性的诸如晶体管的半导体器件。 源极的周围被延伸区域和晕圈区域围绕，漏极的周边被延伸区域和晕圈区域包围，并且具有低杂质浓度的衬底不与源极或漏极接触。 此外，通过栅极绝缘体提供高功函电极，并且消除了从延伸区域进入衬底表面附近的电子。 通过这样的结构，即使在沟道短的情况下，沟道区域的杂质浓度也可以降低，可以获得良好的晶体管特性。

公开(公告)号：US20120146109A1

公开(公告)日：2012-06-14

申请号：US13314326

申请日：2011-12-08

申请人： Shunpei Yamazaki ,  Hiromichi Godo ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Hiromichi Godo ,  Yasuhiko Takemura

IPC分类号： H01L29/78

CPC分类号： H01L29/1083 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device such as a transistor with an excellent OFF characteristic even when a channel is short is provided. A periphery of a source is surrounded by an extension region and a halo region, a periphery of a drain is surrounded by an extension region and a halo region, and a substrate with low impurity concentration is not in contact with the source or the drain. Moreover, a high-work-function electrode is provided via a gate insulator, and electrons entering the vicinity of a surface of the substrate from the extension regions are eliminated. With such a structure, the impurity concentration of the channel region can be decreased even when the channel is short, and a favorable transistor characteristic can be obtained.

摘要翻译： 提供即使在通道短时也具有优异的OFF特性的诸如晶体管的半导体器件。 源极的周围被延伸区域和晕圈区域围绕，漏极的周边被延伸区域和晕圈区域包围，并且具有低杂质浓度的衬底不与源极或漏极接触。 此外，通过栅极绝缘体提供高功函电极，并且消除了从延伸区域进入衬底表面附近的电子。 通过这样的结构，即使在沟道短的情况下，沟道区域的杂质浓度也可以降低，可以获得良好的晶体管特性。

公开(公告)号：US08624321B2

公开(公告)日：2014-01-07

申请号：US12398295

申请日：2009-03-05

申请人： Shunpei Yamazaki ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Hidekazu Miyairi

发明人： Shunpei Yamazaki ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Hidekazu Miyairi

IPC分类号： H01L23/62

CPC分类号： H01L29/78696 ,  H01L29/04 ,  H01L29/66765

摘要： A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer.

摘要翻译： 提供一种薄膜晶体管，其包括覆盖栅极的栅极绝缘层，设置在栅极绝缘层上的微晶半导体层，与微晶半导体层和栅极绝缘层重叠的非晶半导体层，以及一对杂质半导体 提供在非晶半导体层上并且添加赋予一种导电类型的杂质元素以形成源区和漏区的层。 栅极绝缘层具有与微晶半导体层的端部接触的部分相邻的台阶。 在与微晶半导体层接触的部分中，微晶半导体层外部的栅极绝缘层的第二厚度小于其第一厚度。

公开(公告)号：US08492840B2

公开(公告)日：2013-07-23

申请号：US13008285

申请日：2011-01-18

申请人： Shunpei Yamazaki ,  Hiromichi Godo ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Motomu Kurata ,  Mayumi Mikami

发明人： Shunpei Yamazaki ,  Hiromichi Godo ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Motomu Kurata ,  Mayumi Mikami

IPC分类号： H01L27/12

CPC分类号： H01L29/7869

摘要： An object is to provide a semiconductor device including an oxide semiconductor, which maintains favorable characteristics and achieves miniaturization. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, in which the source electrode and the drain electrode each include a first conductive layer, and a second conductive layer having a region which extends in a channel length direction from an end portion of the first conductive layer.

摘要翻译： 本发明的目的是提供一种包含氧化物半导体的半导体器件，其保持有利的特性并实现小型化。 半导体器件包括与氧化物半导体层接触的氧化物半导体层，源极和漏电极，与氧化物半导体层重叠的栅电极，以及设置在氧化物半导体层和栅电极之间的栅极绝缘层， 其中源电极和漏极各自包括第一导电层，以及具有从第一导电层的端部在沟道长度方向上延伸的区域的第二导电层。

公开(公告)号：US08253138B2

公开(公告)日：2012-08-28

申请号：US12263702

申请日：2008-11-03

申请人： Shunpei Yamazaki ,  Satoshi Kobayashi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo

发明人： Shunpei Yamazaki ,  Satoshi Kobayashi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo

IPC分类号： H01L29/04

CPC分类号： H01L29/04 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78696

摘要： A thin film transistor includes a gate electrode, a gate insulating layer covering the gate electrode, a microcrystalline semiconductor layer over the gate insulating layer, an amorphous semiconductor layer over the microcrystalline semiconductor layer, source and drain regions over the amorphous semiconductor layer, source and drain electrodes in contact with and over the source and drain regions, and a part of the amorphous semiconductor layer overlapping with the source and drain regions is thicker than a part of the amorphous semiconductor layer overlapping with a channel formation region. The side face of the source and drain regions and the side face of the amorphous semiconductor form a tapered shape together with an outmost surface of the amorphous semiconductor layer. The taper angle of the tapered shape is such an angle that decrease electric field concentration around a junction portion between the source and drain regions and the amorphous semiconductor layer.

摘要翻译： 薄膜晶体管包括栅电极，覆盖栅电极的栅极绝缘层，栅极绝缘层上的微晶半导体层，微晶半导体层上的非晶半导体层，非晶半导体层上的源极和漏极区，源极和 与源极和漏极区域接触和超过的漏极电极，与源极和漏极区域重叠的部分非晶半导体层比与沟道形成区域重叠的非晶半导体层的一部分更厚。 源极和漏极区域的侧面和非晶半导体的侧面与非晶半导体层的最外表面一起形成锥形形状。 锥形形状的锥角是减小源极和漏极区域与非晶半导体层之间的接合部周围的电场浓度的角度。

公开(公告)号：US20110278571A1

公开(公告)日：2011-11-17

申请号：US13101644

申请日：2011-05-05

申请人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Yusuke Sekine ,  Kazuma Furutani ,  Hiromichi Godo

发明人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Yusuke Sekine ,  Kazuma Furutani ,  Hiromichi Godo

IPC分类号： H01L29/786

CPC分类号： H01L29/7869 ,  G11C16/0433 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/41733 ,  H01L29/78621

摘要： A semiconductor device including a first transistor and a second transistor and a capacitor which are over the first transistor is provided. A semiconductor layer of the second transistor includes an offset region. In the second transistor provided with an offset region, the off-state current of the second transistor can be reduced. Thus, a semiconductor device which can hold data for a long time can be provided.

摘要翻译： 提供了包括在第一晶体管之上的第一晶体管和第二晶体管和电容器的半导体器件。 第二晶体管的半导体层包括偏移区域。 在设置有偏移区域的第二晶体管中，可以减小第二晶体管的截止电流。 因此，可以提供能够长时间保持数据的半导体器件。

公开(公告)号：US20110233542A1

公开(公告)日：2011-09-29

申请号：US13071845

申请日：2011-03-25

申请人： Shunpei Yamazaki ,  Hiromichi Godo

发明人： Shunpei Yamazaki ,  Hiromichi Godo

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1225

摘要： In a transistor including an oxide semiconductor film, a metal oxide film which has a function of preventing electrification and covers a source electrode and a drain electrode is formed in contact with the oxide semiconductor film, and then, heat treatment is performed. Through the heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, whereby the oxide semiconductor film is highly purified. By providing the metal oxide film, generation of a parasitic channel on the back channel side of the oxide semiconductor film in the transistor can be prevented.

摘要翻译： 在包括氧化物半导体膜的晶体管中，形成与氧化物半导体膜接触的具有防止起电并且覆盖源电极和漏电极的功能的金属氧化物膜，然后进行热处理。 通过热处理，有意地从氧化物半导体膜去除氢，水分，羟基或氢化物等杂质，由此氧化物半导体膜被高度纯化。 通过设置金属氧化物膜，可以防止在晶体管中的氧化物半导体膜的背面通道侧产生寄生沟道。

公开(公告)号：US20110127525A1

公开(公告)日：2011-06-02

申请号：US12954222

申请日：2010-11-24

申请人： Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae

发明人： Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae

IPC分类号： H01L29/786

CPC分类号： H01L29/78693 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

摘要： An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm an inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.

摘要翻译： 对于绝缘栅极晶体管的氧化物半导体层，使用已进行脱水或脱氢工序的本征或本质上本征的半导体，以及添加氧以使载流子浓度小于1×10 12 / cm 3的步骤， 其中形成沟道区。 将形成在氧化物半导体层中的沟道的长度设定为0.2μm〜3.0μm，氧化物半导体层和栅极绝缘层的厚度为15nm〜30nm，包括20nm〜50nm ，或分别为15nm〜100nm，10nm〜20nm。 因此，可以抑制短沟道效应，并且在上述通道长度的范围内阈值电压的变化量可以小于0.5V。