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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20090289341A1

    公开(公告)日：2009-11-26

    申请号：US12468284

    申请日：2009-05-19

    申请人： Shunpei Yamazaki ,  Yoshiaki Oikawa ,  Hironobu Shoji ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Masataka Nakada

    发明人： Shunpei Yamazaki ,  Yoshiaki Oikawa ,  Hironobu Shoji ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Masataka Nakada

    IPC分类号： H01L23/02

    CPC分类号： G06K19/07749 ,  G06K19/07735 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1266 ,  H01L27/13 ,  H01Q1/38 ,  H01Q7/00

    摘要： An object is to provide a highly reliable semiconductor device having resistance to external stress and electrostatic discharge while achieving reduction in thickness and size. Another object is to prevent defective shapes and deterioration in characteristics due to external stress or electrostatic discharge in a manufacture process to manufacture a semiconductor device with a high yield. A first insulator and a second insulator facing each other, a semiconductor integrated circuit and an antenna provided between the first insulator and the second insulator facing each other, a conductive shield provided on one surface of the first insulator, and a conductive shield provided on one surface of the second insulator are provided. The conductive shield provided on one surface of the first insulator and the conductive shield provided on one surface of the second insulator are electrically connected.

    摘要翻译： 目的是提供一种具有耐外部应力和静电放电的高度可靠的半导体器件，同时实现厚度和尺寸的减小。 另一个目的是在制造过程中防止由于外部应力或静电放电而导致的形状不良和特性劣化，从而以高产率制造半导体器件。 第一绝缘体和第二绝缘体彼此面对，半导体集成电路和设置在第一绝缘体和第二绝缘体之间彼此面对的天线，设置在第一绝缘体的一个表面上的导电屏蔽和设置在第一绝缘体上的导电屏蔽 提供第二绝缘体的表面。 设置在第一绝缘体的一个表面上的导电屏蔽和设置在第二绝缘体的一个表面上的导电屏蔽电连接。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08237248B2

    公开(公告)日：2012-08-07

    申请号：US12468284

    申请日：2009-05-19

    申请人： Shunpei Yamazaki ,  Yoshiaki Oikawa ,  Hironobu Shoji ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Masataka Nakada

    发明人： Shunpei Yamazaki ,  Yoshiaki Oikawa ,  Hironobu Shoji ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Masataka Nakada

    IPC分类号： H01L23/552

    CPC分类号： G06K19/07749 ,  G06K19/07735 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1266 ,  H01L27/13 ,  H01Q1/38 ,  H01Q7/00

    摘要： An object is to provide a highly reliable semiconductor device having resistance to external stress and electrostatic discharge while achieving reduction in thickness and size. Another object is to prevent defective shapes and deterioration in characteristics due to external stress or electrostatic discharge in a manufacture process to manufacture a semiconductor device with a high yield. A first insulator and a second insulator facing each other, a semiconductor integrated circuit and an antenna provided between the first insulator and the second insulator facing each other, a conductive shield provided on one surface of the first insulator, and a conductive shield provided on one surface of the second insulator are provided. The conductive shield provided on one surface of the first insulator and the conductive shield provided on one surface of the second insulator are electrically connected.

    摘要翻译： 目的是提供一种具有耐外部应力和静电放电的高度可靠的半导体器件，同时实现厚度和尺寸的减小。 另一个目的是在制造过程中防止由于外部应力或静电放电而导致的形状不良和特性劣化，从而以高产率制造半导体器件。 第一绝缘体和第二绝缘体彼此面对，半导体集成电路和设置在第一绝缘体和第二绝缘体之间彼此面对的天线，设置在第一绝缘体的一个表面上的导电屏蔽和设置在第一绝缘体上的导电屏蔽 提供第二绝缘体的表面。 设置在第一绝缘体的一个表面上的导电屏蔽和设置在第二绝缘体的一个表面上的导电屏蔽电连接。

    Semiconductor Device
    5.
    发明申请
    Semiconductor Device 有权
    半导体器件

    公开(公告)号：US20110175083A1

    公开(公告)日：2011-07-21

    申请号：US13004200

    申请日：2011-01-11

    申请人： Yusuke Sekine ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Shunpei Yamazaki

    发明人： Yusuke Sekine ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Shunpei Yamazaki

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

    摘要： A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state (off-state current) between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or to the memory cell by applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another so that the predetermined amount of charge is held in the node. The memory window width is changed by 2% or less, before and after 1×109 times of writing.

    摘要翻译： 半导体器件具有包括写入晶体管的非易失性存储单元，该晶体管包括氧化物半导体，并且在源极和漏极之间的截止状态（截止状态电流）中具有小的漏电流，读取晶体管包括不同于 写晶体管和电容器。 通过向写入晶体管的源电极和漏电极，电容器的一个电极和读取晶体管的栅电极之一彼此电连接的节点施加电位而将数据写入或存储到存储器单元，从而 在节点中保持预定量的电荷。 1×109次写入之前和之后，存储窗宽度改变2％以下。

    Semiconductor memory device having a low off state current and high repeatability
    7.
    发明授权
    Semiconductor memory device having a low off state current and high repeatability 有权
    具有低关断状态电流和高重复性的半导体存储器件

    公开(公告)号：US08698219B2

    公开(公告)日：2014-04-15

    申请号：US13004200

    申请日：2011-01-11

    申请人： Yusuke Sekine ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Shunpei Yamazaki

    发明人： Yusuke Sekine ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Shunpei Yamazaki

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

    摘要： A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state (off-state current) between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or to the memory cell by applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another so that the predetermined amount of charge is held in the node. The memory window width is changed by 2% or less, before and after 1×109 times of writing.

    摘要翻译： 半导体器件具有包括写入晶体管的非易失性存储单元，该晶体管包括氧化物半导体，并且在源极和漏极之间的截止状态（截止状态电流）中具有小的漏电流，读取晶体管包括不同于 写晶体管和电容器。 通过向写入晶体管的源电极和漏电极，电容器的一个电极和读取晶体管的栅电极之一彼此电连接的节点施加电位而将数据写入或存储到存储器单元，从而 在节点中保持预定量的电荷。 1×109次写入之前和之后，存储窗宽度改变2％以下。

    Wireless processor, wireless memory, information system, and semiconductor device
    10.
    发明授权
    Wireless processor, wireless memory, information system, and semiconductor device 有权
    无线处理器，无线存储器，信息系统和半导体器件

    公开(公告)号：US08716814B2

    公开(公告)日：2014-05-06

    申请号：US11571859

    申请日：2005-07-07

    申请人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Jun Koyama ,  Yutaka Shionoiri

    发明人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Jun Koyama ,  Yutaka Shionoiri

    IPC分类号： H01L27/14

    CPC分类号： H01L27/1222 ,  G06K19/0723 ,  H01L23/5387 ,  H01L23/66 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/13 ,  H01L29/78621 ,  H01L29/78648 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.

    摘要翻译： 本发明提供一种处理器，其通过在对热敏感的基板（例如塑料基板或塑料膜基板）上形成使用多晶半导体的高功能集成电路。 此外，本发明提供一种无线发送和接收电力或信号的无线处理器，无线存储器及其信息处理系统。 根据本发明，一种信息处理系统包括一个元件形成区域，该元件形成区域包括晶体管，该晶体管至少具有由半导体膜形成的沟道形成区域，半导体膜分隔成10至200nm的厚度的岛状物以及天线。 晶体管固定在柔性基板上。 其中形成包括元件形成区域的高功能集成电路并且半导体器件通过天线发送和接收数据的无线处理器。