公开(公告)号：US11527491B2

公开(公告)日：2022-12-13

申请号：US17337770

申请日：2021-06-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chun-Tang Lin ,  Shou-Qi Chang ,  Yu-Hsiang Hsieh

IPC: H01L23/00 ,  H01L23/14 ,  H01L25/065 ,  H01L23/498 ,  H01L23/13 ,  H01L23/31

Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.

公开(公告)号：US20210296261A1

公开(公告)日：2021-09-23

申请号：US17337770

申请日：2021-06-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chun-Tang Lin ,  Shou-Qi Chang ,  Yu-Hsiang Hsieh

IPC: H01L23/00 ,  H01L23/14 ,  H01L25/065 ,  H01L23/498 ,  H01L23/13

Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.

公开(公告)号：US20180254250A1

公开(公告)日：2018-09-06

申请号：US15624590

申请日：2017-06-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chun-Tang Lin ,  Shou-Qi Chang ,  Yu-Hsiang Hsieh

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L29/06 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.

公开(公告)号：US12046494B2

公开(公告)日：2024-07-23

申请号：US17988286

申请日：2022-11-16

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wu-Hung Yen ,  Yi-Hsien Huang ,  Chun-Tang Lin ,  Shu-Hua Chen ,  Shou-Qi Chang

IPC: H01L21/67

CPC classification number: H01L21/67271 ,  H01L21/67144

Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.

公开(公告)号：US20230076941A1

公开(公告)日：2023-03-09

申请号：US17988286

申请日：2022-11-16

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wu-Hung Yen ,  Yi-Hsien Huang ,  Chun-Tang Lin ,  Shu-Hua Chen ,  Shou-Qi Chang

IPC: H01L21/67

Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.

公开(公告)号：US11532495B2

公开(公告)日：2022-12-20

申请号：US17073783

申请日：2020-10-19

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wu-Hung Yen ,  Yi-Hsien Huang ,  Chun-Tang Lin ,  Shu-Hua Chen ,  Shou-Qi Chang

IPC: H01L21/67

Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.

公开(公告)号：US20220068680A1

公开(公告)日：2022-03-03

申请号：US17073783

申请日：2020-10-19

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wu-Hung Yen ,  Yi-Hsien Huang ,  Chun-Tang Lin ,  Shu-Hua Chen ,  Shou-Qi Chang

IPC: H01L21/67

Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.

公开(公告)号：US11056442B2

公开(公告)日：2021-07-06

申请号：US15624590

申请日：2017-06-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chun-Tang Lin ,  Shou-Qi Chang ,  Yu-Hsiang Hsieh

IPC: H01L23/00 ,  H01L23/14 ,  H01L25/065 ,  H01L23/498 ,  H01L23/13 ,  H01L23/31

Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.