摘要:
An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要:
An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要:
An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要:
A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
摘要:
A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
摘要:
An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要:
A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a power management die bonded to the CPU die in a three dimensional packaging layout.
摘要:
In some embodiments, the invention includes a system having a processor and control circuitry. The control circuitry controls a setting of a body bias signal to control body biases provided in the processor to at least partially control a parameter of the processor, wherein the control circuitry controls the setting responsive to processor signal resulting for execution of software. The control circuitry may further control settings of a supply voltage signal and a clock signal to control the parameter. More than one parameter may be controlled. Examples of the parameters include performance, power consumption, and temperature.
摘要:
In some embodiments, the invention includes a system having first and second domains. The system includes a first performance detection circuitry including some transistors of the first domain to provide a first performance rating signal indicative of transistor switching rates of the first domain. The system includes second performance detection circuitry including some transistors of the second domain to provide a second performance rating signal indicative of transistor switching rates the second domain. The system further includes control circuitry to receive the first and second performance rating signals and control a setting for a body bias signal for the first domain and control a setting for a body bias signal for the second domain responsive to the performance rating signals. In some embodiments, the control circuitry also provides supply voltage signals and clock signals responsive to the performance signals. The first and second domains may have clock signals with the same frequency and the bias values are set such that the transistors of the first and second domains can switch properly while the first and second domains have the clock signals and wherein one of the first and second domains operates at less than optimal performance.
摘要:
In one embodiment, a semiconductor circuit includes a first group of field effect transistors having a body and parameters including a net channel doping level DL1. The circuit also includes a conductor to provide a first voltage to the body to forward body bias the first group of transistors, the first group of transistors having a forward body bias threshold voltage (VtFBB) when forward body biased, wherein DL1 is at least 25% higher than a net channel doping level in the first group of transistors that would result in a zero body bias threshold voltage equal to VtFBB, with the parameters other than the net channel doping level being unchanged. In another embodiment, the semiconductor circuit includes a first circuit including a first group of field effect transistors having a body. The circuit also includes a first voltage source to provide a first voltage to the body such that the field effect transistors have a forward body bias, the first voltage being at a level leading to the circuit experiencing a reduced rate of soft error failures as compared to when the circuit is not forward biased.