公开(公告)号：US12028088B2

公开(公告)日：2024-07-02

申请号：US17850235

申请日：2022-06-27

Applicant: Socionext Inc.

Inventor： Jayaraman Kumar ,  Kenneth Stephen Hunt

IPC: H03M1/38 ,  H03M1/06 ,  H03M1/18 ,  H03M1/46

CPC classification number: H03M1/38 ,  H03M1/0697 ,  H03M1/183 ,  H03M1/462 ,  H03M1/468

Abstract: Analogue-to-digital converter, ADC, circuitry, including: an analogue input terminal; a comparator having first and second comparator-input terminals; and successive-approximation control circuitry to apply a potential difference across the first and second comparator-input terminals based on an input voltage signal, and to control the potential difference for a series of successive approximation operations to cause the comparator to test in each successive approximation operation whether a magnitude of an analogue input voltage signal is larger or smaller than a corresponding test value, the test value for each successive approximation operation being, dependent on a comparison result generated by the comparator in the preceding approximation operation, bigger or smaller than the test value for the preceding approximation operation by a difference amount configured for that successive approximation operation.

公开(公告)号：US12126355B2

公开(公告)日：2024-10-22

申请号：US17859658

申请日：2022-07-07

Applicant: Socionext Inc.

Inventor： Jayaraman Kumar ,  Kenneth Stephen Hunt

IPC: H03M1/66 ,  H03M1/38 ,  H03M1/06 ,  H03M1/12

CPC classification number: H03M1/66 ,  H03M1/38 ,  H03M1/0604 ,  H03M1/12

Abstract: Mixed-signal circuitry including a set of capacitive digital-to-analogue converter, CDAC, units for carrying out digital-to-analogue conversion operations to convert respective digital values into corresponding analogue values; and control circuitry, where: each CDAC unit includes an array of capacitors at least some of which are configured to be individually-switched dependent on the digital values, the capacitors configured to have nominal capacitances; a given capacitor of the array of capacitors in each of the CDAC units is a target capacitor; the set of CDAC units includes a plurality of sub-sets of CDAC units; at least one of the target capacitors per sub-set of CDAC units is a variable capacitor, controllable by the control circuitry to have any one of a plurality of nominal capacitances defined by the configuration of that capacitor.

公开(公告)号：US12149239B2

公开(公告)日：2024-11-19

申请号：US18149421

申请日：2023-01-03

Applicant: Socionext Inc.

Inventor： Kenneth Stephen Hunt

IPC: H03K17/687 ,  H03K17/06 ,  H03K19/08 ,  H03M1/66

Abstract: A switched current source circuit, comprising first and second voltage source nodes; a load; a current source; and capacitor switching circuitry comprising a load node, a capacitor and a plurality of switches configured, based on a control signal, to adopt a biasing configuration followed by an active configuration, wherein in the biasing configuration, the load node is conductively connected to the second voltage source node to bias a voltage level at the load node, and the capacitor is connected so that it at least partly charges; and in the active configuration, the load node is conductively connected via the load to the first voltage source node, and via the capacitor to the current source to increase a potential difference between the first voltage source node and the load node.

公开(公告)号：US12107592B2

公开(公告)日：2024-10-01

申请号：US17864966

申请日：2022-07-14

Applicant: Socionext Inc.

Inventor： Kenneth Stephen Hunt ,  Antoine Morineau ,  Aadilhussain Maniyar

IPC: H03M1/06 ,  H03K5/24

CPC classification number: H03M1/0607 ,  H03K5/2481 ,  H03K5/249

Abstract: A comparator including: first and second input transistors connected to control signals at first and second nodes of the comparator; latch circuitry; at least one controllable offset-correction component having an input terminal and connected to control the signal at one of the first and second nodes based on an offset-correction signal provided at its input terminal; for each controllable offset-correction component, an offset correction circuit configured to provide the offset-correction signal provided at its input terminal; and control circuitry. The control circuitry controls the at least one offset-correction circuit to: control an amount by which the offset-correction signal is adjusted; and/or in a bypass operation, connect the input terminal of the at least one controllable offset-correction component to a bypass-operation reference voltage supply; and/or in a maintenance operation, control the charging-operation voltage supply and/or the bypass-operation voltage supply to control leakage of the charge stored on the holding capacitor.