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    Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
    1.
    发明授权
    Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom 失效
    电可擦除的直接可重写的多单元单元存储元件和由其制造的阵列

    公开(公告)号：US5534711A

    公开(公告)日：1996-07-09

    申请号：US423484

    申请日：1995-04-19

    申请人： Stanford R. Ovshinsky ,  David A. Strand ,  Wolodymyr Czubatyj ,  Patrick Klersy

    发明人： Stanford R. Ovshinsky ,  David A. Strand ,  Wolodymyr Czubatyj ,  Patrick Klersy

    IPC分类号： G11C11/56 ,  G11C16/02 ,  H01L27/24 ,  H01L45/00

    CPC分类号： G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  G11C13/04 ,  G11C2213/72

    摘要： The present invention comprises an electrically operated, directly overwritable, multibit, single-cell memory element. The memory element includes a volume of memory material which defines the single cell memory element. The memory material is characterized by: (1) a large dynamic range of electrical resistance values; and (2) the ability to be set at one of a plurality of resistance values within said dynamic range in response to selected electrical input signals so as to provide said single cell with multibit storage capabilities. The memory element also includes a pair of spacedly disposed contacts for supplying the electrical input signal to set the memory material to a selected resistance value within the dynamic range. At least a filamentary portion of the singIe cell memory element being setable, by the selected electrical signal to any resistance value in said dynamic range, regardless of the previous resistance value of said material. The memory element further includes a filamentary portion controlling means disposed between the volume of memory material and at least one of the spacedly disposed contacts. The controlling means defining the size and position of the filamentary portion during electrical formation of the memory element and limiting the size and confining the location of the filamentary portion during use of the memory element, thereby providing for a high current density within the filamentary portion of the single cell memory element upon input of a very low total current electrical signal to the spacedly disposed contacts.

    摘要翻译： 本发明包括电操作的直接覆盖的多位单个单元存储元件。 存储元件包括限定单个单元存储元件的一定量的存储器材料。 记忆材料的特征在于：（1）电阻值的大动态范围; 以及（2）响应于所选择的电输入信号在所述动态范围内被设置为多个电阻值之一的能力，以便向所述单个单元提供多位存储能力。 存储元件还包括一对间隔设置的触点，用于提供电输入信号以将存储器材料设置在动态范围内的所选电阻值。 所述单元存储元件的至少一个细长部分可通过所选择的电信号被设置成所述动态范围内的任何电阻值，而与所述材料的先前电阻值无关。 存储元件还包括设置在存储器材料体积与间隔设置的触点中的至少一个之间的丝状部分控制装置。 控制装置在存储元件的电气形成期间限定丝状部分的尺寸和位置，并且在存储元件的使用期间限制尺寸并限制丝状部分的位置，由此提供丝网部分内的高电流密度 当输入非常低的总电流电信号到间隔布置的触点时，单个单元存储元件。

    Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
    6.
    发明授权
    Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom 失效
    电可擦除的直接可重写的多单元单元存储元件和由其制造的阵列

    公开(公告)号：US5406509A

    公开(公告)日：1995-04-11

    申请号：US46249

    申请日：1993-04-12

    申请人： Stanford R. Ovshinsky ,  Qiuyi Ye ,  David A. Strand ,  Wolodymyr Czubatyj

    发明人： Stanford R. Ovshinsky ,  Qiuyi Ye ,  David A. Strand ,  Wolodymyr Czubatyj

    IPC分类号： G11C11/56 ,  G11C16/02 ,  H01L27/24 ,  H01L45/00 ,  G11C17/14

    CPC分类号： G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  G11C13/04 ,  G11C2213/72

    摘要： The present invention comprises an electrically operated, directly overwritable, multibit, single-cell memory element. The memory element includes a volume of memory material which defines the single cell memory element. The memory material is characterized by: (1) a large dynamic range of electrical resistance values; and (2) the ability to be set at one of a plurality of resistance values within said dynamic range in response to selected electrical input signals so as to provide said single cell with multibit storage capabilities. The memory element also includes a pair of spacedly disposed contacts for supplying the electrical input signal to set the memory material to a selected resistance value within the dynamic range. At least a filamentary portion of the single cell memory element being setable, by the selected electrical signal to any resistance value in said dynamic range, regardless of the previous resistance value of said material. The memory element further includes a filamentary portion controlling means disposed between the volume of memory material and at least one of the spacedly disposed contacts. The controlling means defining the size and position of the filamentary portion during electrical formation of the memory element and limiting the size and confining the location of the filamentary portion during use of the memory element, thereby providing for a high current density within the filamentary portion of the single cell memory element upon input of a very low total current electrical signal to the spacedly disposed contacts.

    摘要翻译： 本发明包括电操作的直接覆盖的多位单个单元存储元件。 存储元件包括限定单个单元存储元件的一定量的存储器材料。 记忆材料的特征在于：（1）电阻值的大动态范围; 以及（2）响应于所选择的电输入信号在所述动态范围内被设置为多个电阻值之一的能力，以便向所述单个单元提供多位存储能力。 存储元件还包括一对间隔设置的触点，用于提供电输入信号以将存储器材料设置在动态范围内的所选电阻值。 所述单个单元存储元件的至少一个细长部分可被所选择的电信号设定到所述动态范围内的任何电阻值，而与所述材料的先前电阻值无关。 存储元件还包括设置在存储器材料体积与间隔设置的触点中的至少一个之间的丝状部分控制装置。 控制装置在存储元件的电气形成期间限定丝状部分的尺寸和位置，并且在存储元件的使用期间限制尺寸并限制丝状部分的位置，由此提供丝网部分内的高电流密度 当输入非常低的总电流电信号到间隔布置的触点时，单个单元存储元件。

    Electrically erasable memory elements having improved set resistance stability
    8.
    发明授权
    Electrically erasable memory elements having improved set resistance stability 失效
    具有改进的电阻稳定性的电可擦除存储元件

    公开(公告)号：US5414271A

    公开(公告)日：1995-05-09

    申请号：US789234

    申请日：1991-11-07

    申请人： Stanford R. Ovshinsky ,  Stephen J. Hudgens ,  Wolodymyr Czubatyj ,  David A. Strand ,  Guy C. Wicker

    发明人： Stanford R. Ovshinsky ,  Stephen J. Hudgens ,  Wolodymyr Czubatyj ,  David A. Strand ,  Guy C. Wicker

    IPC分类号： G11C11/56 ,  G11C16/02 ,  H01L27/24 ,  H01L45/00

    CPC分类号： G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1625 ,  G11C13/04 ,  G11C2213/72

    摘要： A solid state, directly overwritable, electronic, non-volatile, high density, low cost, low energy, high speed, readily manufacturable, multibit single cell memory or control array based upon the novel switching characteristics provided by said unique class of semiconductor materials characterized by a large dynamic range of reversible Fermi level positions. The memory or control elements from which the array is fabricated exhibit orders of magnitude higher switching speeds at remarkably reduced energy levels. The novel memory elements of the instant invention are in turn characterized, inter alia, by numerous stable and non-volatile detectable configurations of local atomic and/or electrode order, which configurations can be selectively and repeatably accessed by electric input signals of yawing energy level. The memory elements are further characterized by enhanced stability, which stability is achieved through the use of compositional modulation of the semiconductor material from which the memory elements are fabricated.

    摘要翻译： 基于由所述独特类型的半导体材料提供的新颖的开关特性，固态，直接可重写的，电子的，非易失性的，高密度的，低成本的，低能量的，高速的，容易制造的多单元单元存储器或控制阵列 通过可逆的费米能级位置的大动态范围。 制造阵列的存储器或控制元件在显着降低的能量水平下显示出更高的开关速度的数量级。 本发明的新颖的记忆元件又特别包括局部原子和/或电极顺序的许多稳定和非易失性的可检测配置，这些配置可以通过偏转能级的电输入信号来选择性地和重复地访问 。 存储元件的特征还在于增强的稳定性，其通过使用制造存储元件的半导体材料的组成调制来实现稳定性。

    Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life
    9.
    发明授权
    Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life 失效
    电可擦除存储元件具有降低的开关电流要求和增加的写入/擦除周期寿命

    公开(公告)号：US5341328A

    公开(公告)日：1994-08-23

    申请号：US898635

    申请日：1992-06-15

    申请人： Stanford R. Ovshinsky ,  Stephen J. Hudgens ,  Wolodymyr Czubatyj ,  David A. Strand ,  Guy C. Wicker

    发明人： Stanford R. Ovshinsky ,  Stephen J. Hudgens ,  Wolodymyr Czubatyj ,  David A. Strand ,  Guy C. Wicker

    IPC分类号： G11C11/56 ,  G11C16/02 ,  H01L27/24 ,  H01L45/00

    CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/115 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1625 ,  G11C13/04 ,  G11C2213/72

    摘要： Disclosed herein is a solid state, directly overwritable, non-volatile, high density, low cost, low energy, high speed, readily manufacturable, single cell memory element having reduced switching current requirements and increased write/erase cycle life. The structurally modified memory element includes an electrical contact formed of amorphous silicon, either alone or in combination with a layer of amorphous carbon layer. The memory element exhibits orders of magnitude higher switching speeds at remarkably reduced switching energy levels. The novel memory elements of the instant invention are further characterized, inter alia, by at least two stable and non-volatile detectable configurations of local atomic and/or electronic order, which configurations can be selectively and repeatably accessed by electrical input signals of designated energies. The reduced switching current requirements and an increased write/erase cycle life are achieved by structurally modifying the electrical contact with the aforementioned layer of amorphous silicon.

    摘要翻译： 本文公开了具有降低的开关电流要求和增加的写入/擦除循环寿命的固态，直接可重写，非易失性，高密度，低成本，低能量，高速度，容易制造的单电池存储元件。 结构改进的记忆元件包括由非晶硅形成的电接触，单独或与无定形碳层组合。 存储元件在显着降低的开关能量水平下显示出更高的开关速度的数量级。 本发明的新颖的记忆元件尤其通过局部原子和/或电子顺序的至少两个稳定和非易失性可检测配置来进一步表征，这些配置可以通过指定能量的电输入信号被选择性地和重复地访问 。 通过结构上改变与上述非晶硅层的电接触来实现降低的开关电流要求和增加的写入/擦除周期寿命。