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1.发明授权Method for controlling the supply voltage for an integrated circuit and an apparatus with a voltage regulation module and an integrated circuit 失效用于控制集成电路的电源电压的方法和具有电压调节模块和集成电路的装置公开(公告)号：US08471624B2
公开(公告)日：2013-06-25
申请号：US13037343
申请日：2011-02-28
IPC分类号： G05F3/02
CPC分类号： G05F1/56
摘要： The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module (10) via the voltage supply line. The supply voltage is composed of a reference voltage and a number of additional voltage levels. The reference voltage is defined by a voltage source and controlled by the integrated circuit via the bus, and the number of additional voltage levels is determined by the integrated circuit and send to the voltage regulation module via the sense line. Further the present invention relates to a corresponding apparatus with a voltage regulation module and an integrated circuit.
摘要翻译： 本发明涉及一种用于控制集成电路的电源电压的方法，该集成电路通过感测线，电压供应线和总线连接到电压调节模块，其中电源电压由电压调节模块（10 ）通过电源线。 电源电压由参考电压和多个附加电压电平组成。 参考电压由电压源定义，并通过总线由集成电路控制，附加电压电平的数量由集成电路确定，并通过感测线发送到电压调节模块。 此外，本发明涉及具有电压调节模块和集成电路的相应装置。
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2.发明申请METHOD FOR CONTROLLING THE SUPPLY VOLTAGE FOR AN INTEGRATED CIRCUIT AND AN APPARATUS WITH A VOLTAGE REGULATION MODULE AND AN INTEGRATED CIRCUIT 失效用于控制集成电路的电源电压的方法和具有电压调节模块和集成电路的装置公开(公告)号：US20120218031A1
公开(公告)日：2012-08-30
申请号：US13037343
申请日：2011-02-28
IPC分类号： G05F1/10
CPC分类号： G05F1/56
摘要： The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module (10) via the voltage supply line. The supply voltage is composed of a reference voltage and a number of additional voltage levels. The reference voltage is defined by a voltage source and controlled by the integrated circuit via the bus, and the number of additional voltage levels is determined by the integrated circuit and send to the voltage regulation module via the sense line. Further the present invention relates to a corresponding apparatus with a voltage regulation module and an integrated circuit.
摘要翻译： 本发明涉及一种用于控制集成电路的电源电压的方法，该集成电路通过感测线，电压供应线和总线连接到电压调节模块，其中电源电压由电压调节模块（10 ）通过电源线。 电源电压由参考电压和多个附加电压电平组成。 参考电压由电压源定义，并通过总线由集成电路控制，附加电压电平的数量由集成电路确定，并通过感测线发送到电压调节模块。 此外，本发明涉及具有电压调节模块和集成电路的相应装置。
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3.发明申请METHOD FOR CONTROLLING THE SUPPLY VOLTAGE FOR AN INTEGRATED CIRCUIT AND AN APPARATUS WITH A VOLTAGE REGULATION MODULE AND AN INTEGRATED CIRCUIT 失效用于控制集成电路的电源电压的方法和具有电压调节模块和集成电路的装置公开(公告)号：US20130113545A9
公开(公告)日：2013-05-09
申请号：US13037343
申请日：2011-02-28
IPC分类号： G05F1/10
CPC分类号： G05F1/56
摘要： The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module (10) via the voltage supply line. The supply voltage is composed of a reference voltage and a number of additional voltage levels. The reference voltage is defined by a voltage source and controlled by the integrated circuit via the bus, and the number of additional voltage levels is determined by the integrated circuit and send to the voltage regulation module via the sense line. Further the present invention relates to a corresponding apparatus with a voltage regulation module and an integrated circuit.
摘要翻译： 本发明涉及一种用于控制集成电路的电源电压的方法，该集成电路通过感测线，电压供应线和总线连接到电压调节模块，其中电源电压由电压调节模块（10 ）通过电源线。 电源电压由参考电压和多个附加电压电平组成。 参考电压由电压源定义，并通过总线由集成电路控制，附加电压电平的数量由集成电路确定，并通过感测线发送到电压调节模块。 此外，本发明涉及具有电压调节模块和集成电路的相应装置。
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4.发明申请METHOD FOR CONTROLLING THE SUPPLY VOLTAGE FOR AN INTEGRATED CIRCUIT AND AN APPARATUS WITH A VOLTAGE REGULATION MODULE AND AN INTEGRATED CIRCUIT 审中-公开用于控制集成电路的电源电压的方法和具有电压调节模块和集成电路的装置公开(公告)号：US20100013446A1
公开(公告)日：2010-01-21
申请号：US12174902
申请日：2008-07-17
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module (10) via the voltage supply line. The supply voltage is composed of a reference voltage and a number of additional voltage levels. The reference voltage is defined by a voltage source and controlled by the integrated circuit via the bus, and the number of additional voltage levels is determined by the integrated circuit and send to the voltage regulation module via the sense line. Further the present invention relates to a corresponding apparatus with a voltage regulation module and an integrated circuit.
摘要翻译： 本发明涉及一种用于控制集成电路的电源电压的方法，该集成电路通过感测线，电压供应线和总线连接到电压调节模块，其中电源电压由电压调节模块（10 ）通过电源线。 电源电压由参考电压和多个附加电压电平组成。 参考电压由电压源定义，并通过总线由集成电路控制，附加电压电平的数量由集成电路确定，并通过感测线发送到电压调节模块。 此外，本发明涉及具有电压调节模块和集成电路的相应装置。
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5.发明申请Signal Delay Element, Method and Integrated Circuit Device for Frequency Adjustment of Electronic Signals 有权用于电子信号频率调整的信号延迟元件，方法和集成电路装置公开(公告)号：US20090021288A1
公开(公告)日：2009-01-22
申请号：US12045894
申请日：2008-03-11
申请人： Florian Braun , Cedric Lichtenau , Thomas Pflueger , Ulrich Weiss
发明人： Florian Braun , Cedric Lichtenau , Thomas Pflueger , Ulrich Weiss
IPC分类号： H03B19/00
CPC分类号： H03K5/156 , H03K5/135 , H03K2005/00052 , H03L7/07 , H03L7/0814
摘要： The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.
摘要翻译： 本发明涉及电子信号的频率调整。 该方法包括以下步骤：提供具有第一频率的频率发生器的输出信号作为提供所述信号延迟元件的所述输入信号的边沿的信号延迟元件的输入信号; 通过向所述输入信号的每个周期添加延迟来延迟所述输入信号，直到信号延迟元件的延迟的输出信号与所述输入信号的边沿对准。
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公开(公告)号：US07106110B2
公开(公告)日：2006-09-12
申请号：US10710681
申请日：2004-07-28
申请人： Miles G. Canada , Erwin B. Cohen , Jay G. Heaslip , Cedric Lichtenau , Thomas Pflueger , Mathew I. Ringler
发明人： Miles G. Canada , Erwin B. Cohen , Jay G. Heaslip , Cedric Lichtenau , Thomas Pflueger , Mathew I. Ringler
IPC分类号： H03B19/00
CPC分类号： G06F1/08 , G06F1/324 , Y02D10/126
摘要： A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for a predetermined number of cycles; and setting the clock frequency to the second frequency after the predetermined number of cycles.
摘要翻译： 一种将集成电路装置的时钟频率从第一频率转换到第二频率的系统和方法，包括根据抖动模式在第一频率和第二频率之间交替，交替发生预定数量的周期; 并且在预定次数的周期之后将时钟频率设置为第二频率。
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公开(公告)号：US20050104637A1
公开(公告)日：2005-05-19
申请号：US10707066
申请日：2003-11-19
申请人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Mathew Ringler , Gerard Salem , Peter Sandon , Dana Thygesen , Ulrich Weiss
发明人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Mathew Ringler , Gerard Salem , Peter Sandon , Dana Thygesen , Ulrich Weiss
IPC分类号： H03L7/06
CPC分类号： H03L7/06
摘要： A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.
摘要翻译： 能够将多个处理器（A，B）的频率分频计数器（124A，124BB）同时复位的同步系统为零，而不管分频频率 信号（Mclk / n信号（168A，168B）），并且与处理器中的Mclk / n信号经历的时钟网格延迟的大小无关。 同步系统包括用于在未分割信号中模拟的每个处理器的网格延迟电路（176A，176BB）（Mclk / 1信号（136 < / SUB>，136 B））由该处理器中的Mclk / n信号经历的时钟网格延迟，以便提供Lclk信号（172 ，172 B ）。 相位检测器检测Mclk / n信号和Sysclk信号之间的相位偏移（112），并将异步偏移信号（194A，192B）发送到计数器 基于偏移信号将再分配计数器复位为零的重新设置器（196A，196BB）。
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公开(公告)号：US07865749B2
公开(公告)日：2011-01-04
申请号：US10595520
申请日：2003-10-31
IPC分类号： G06F1/32
摘要： A method and apparatus for changing a clock frequency in a system (10) comprising a plurality of synchronous integrated circuit chips (12, 14, 16), and a circuit (20) for implementing the frequency change. The method includes: detecting a change in processing requirements in one of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that a clock frequency change is to occur; achieving a quiescent bus state in each of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that the clock frequency change can occur; and changing the clock frequency of the plurality of integrated circuit chips.
摘要翻译： 一种用于改变包括多个同步集成电路芯片（12,14,16）的系统（10）中的时钟频率的方法和装置，以及用于实现频率变化的电路（20）。 该方法包括：检测多个同步集成电路芯片之一中处理要求的变化; 通知多个同步集成电路芯片发生时钟频率变化; 在所述多个同步集成电路芯片的每一个中实现静态总线状态; 通知多个同步集成电路芯片可能发生时钟频率变化; 以及改变多个集成电路芯片的时钟频率。
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9.发明授权Providing accurate time-based counters for scaling operating frequencies of microprocessors 失效提供精确的时间计数器来缩放微处理器的工作频率公开(公告)号：US07602874B2
公开(公告)日：2009-10-13
申请号：US11340449
申请日：2006-01-26
申请人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Martin Recktenwald , Andreas Schmid
发明人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Martin Recktenwald , Andreas Schmid
IPC分类号： H04L7/00
摘要： A mechanism provides accurate time-based counters for scaling operating frequencies of microprocessors. The mechanism makes use of a time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of the clock generation circuit of the microprocessor and is used to feed the external and internal timebase logic as well as a timebase accumulator counter. The timebase accumulator counter accumulates the tick events from the timebase logic between two core clocks. The accumulated value is transferred to the core clock domain on every clock edge of a scalable clock and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment.
摘要翻译： 一种机制提供了精确的基于时间的计数器来缩放微处理器的工作频率。 该机制利用基于时间的计数器电路配置，其中从微处理器的时钟产生电路的PLL导出固定频率时钟，并且用于馈送外部和内部时基逻辑以及时基累加器计数器。 时基累加器计数器从两个核心时钟之间的时基逻辑累加tick事件。 累加值在可伸缩时钟的每个时钟沿传输到核心时钟域，然后累加器复位。 因为在累加器复位之前累积的刻度被传送到核心时钟域，所以使用说明性实施例的电路不会丢失任何刻度。
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10.发明申请SEMICONDUCTOR CHIP WITH A PLURALITY OF SCANNABLE STORAGE ELEMENTS AND A METHOD FOR SCANNING STORAGE ELEMENTS ON A SEMICONDUCTOR CHIP 有权具有多重可扫描存储元件的半导体芯片和用于扫描半导体芯片上的存储元件的方法公开(公告)号：US20080276140A1
公开(公告)日：2008-11-06
申请号：US12042944
申请日：2008-03-05
申请人： Tobias Gemmeke , Christoph Jaeschke , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Jochen Preiss
发明人： Tobias Gemmeke , Christoph Jaeschke , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Jochen Preiss
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318575
摘要： A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.
摘要翻译： 分为功率域的半导体芯片，至少一个功率域被单独激活或去激活，并且可扫描存储元件的至少一部分互连到一个或多个扫描链。 至少一个扫描链被连续地分成扫描链部分，并且扫描链部分被布置在一个功率域内。 对于至少一个扫描链部分，提供旁路线以通过扫描数据，并且提供至少一个选择单元用于根据相应功率域的激活或去激活状态在旁路线和对应的扫描链部分之间进行选择 。
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