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公开(公告)号：US06475851B1
公开(公告)日：2002-11-05
申请号：US09124478
申请日：1998-07-29
IPC分类号： H01L218238
CPC分类号： H01L21/765 , H01L21/823481 , H01L27/0207 , H01L27/088 , H01L27/10805 , Y10T307/839
摘要： Adjacent unassociated field-effect transistors are formed from a single continuous layer of uniformly doped material in a semiconductor substrate. An insulating layer is formed over the active layer. A number of gates in a conductive layer define the transistors. Forming a connection between one of the gates and a reference potential forms a boundary between the unassociated transistors across the active material by preventing carrier transport thereacross.
摘要翻译： 相邻的非相关场效应晶体管由半导体衬底中的均匀掺杂材料的单个连续层形成。 在有源层上形成绝缘层。 导电层中的多个栅极限定晶体管。 在一个栅极和参考电位之间形成连接，通过防止跨越其的载流子传输，形成跨过活性材料的非相关晶体管之间的边界。
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公开(公告)号：US06242782B1
公开(公告)日：2001-06-05
申请号：US09124283
申请日：1998-07-29
IPC分类号： H01L2994
CPC分类号： H01L21/765 , H01L21/823481 , H01L27/0207 , H01L27/088 , H01L27/10805 , Y10T307/839
摘要： The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.
摘要翻译： 连接在半导体衬底中形成的相邻晶体管的非相关有源区的隔离栅的提供不需要额外的工艺步骤来提供相邻晶体管的有效隔离。 隔离栅极连接到参考，以确保未形成非相关活动区域之间的通道，并提供有效的隔离。 相邻的晶体管被交叉耦合以形成用于动态随机存取存储器件的读出放大器。
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公开(公告)号：US6015729A
公开(公告)日：2000-01-18
申请号：US919849
申请日：1997-08-28
CPC分类号： H01L27/105 , H01L27/0623 , H01L27/0629 , H01L28/40
摘要： A multilayer decoupling capacitor structure is disclosed, having a first decoupling capacitor with one electrode formed in a conductively doped silicon substrate and a second electrode made of conductively doped polysliicon. A third bifurcated conductive layer disposed above the second electrode in conjunction with a fourth conductive layer above the third layer form a second and third decoupling capacitor. The first decoupling capacitor serves to decouple circuitry associated with dynamic random access memory cells, while the second and third decoupling capacitors provide decoupling for further circuitry.
摘要翻译： 公开了一种多层去耦电容器结构，其具有在导电掺杂硅衬底中形成的一个电极的第一去耦电容器和由导电掺杂多晶硅制成的第二电极。 配置在第二电极上方的第三分支导电层与第三层上方的第四导电层结合形成第二和第三去耦电容器。 第一去耦电容器用于去耦合与动态随机存取存储器单元相关的电路，而第二和第三去耦电容器为进一步的电路提供去耦。
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公开(公告)号：US5834820A
公开(公告)日：1998-11-10
申请号：US543160
申请日：1995-10-13
IPC分类号： H01L21/765 , H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L21/765 , H01L27/0207 , H01L27/088 , H01L27/10805 , H01L21/823481 , Y10T307/839
摘要： The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.
摘要翻译： 连接在半导体衬底中形成的相邻晶体管的非相关有源区的隔离栅的提供不需要额外的工艺步骤来提供相邻晶体管的有效隔离。 隔离栅极连接到参考，以确保未形成非相关活动区域之间的通道，并提供有效的隔离。 相邻的晶体管被交叉耦合以形成用于动态随机存取存储器件的读出放大器。
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5.再颁专利Inverting output driver circuit for reducing electron injection into the substrate 失效用于减少电子注入基板的反相输出驱动电路
公开(公告)号：USRE35764E
公开(公告)日：1998-04-07
申请号：US713757
申请日：1996-09-13
IPC分类号： H03K17/16 , H03K17/08 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0948 , H03K19/20
CPC分类号： H03K19/00361 , H03K19/00315
摘要： A new inverting output driver circuit is disclosed that reduces electron injection into the substrate by the drain of the circuit's pull-up field effect transistor. This is accomplished by adding additional circuitry that allows the gate voltage of the pull-up transistor to track the source voltage. The output circuit makes use of an inverter having an output node (hereinafter the intermediate node) coupled to V.sub.CC through a first P-channel FET, and to ground through first and second series coupled N-channel FETs, respectively. The gates of the P-channel FET and the first N-channel FET are coupled to and controlled by an input node. The inverter output node controls the gate of third N-channel FET, through which a final output node is coupled to V.sub.CC. The intermediate node is coupled to the final output node through a fourth N-channel FET, the gate of which is held at ground potential. The gate of the second N-channel FET is coupled to V.sub.CC through a second P-channel FET and to the final output node through a fifth N-channel FET which has much greater drive than the second P-channel FET; the gates of both the second P-channel FET and the fifth N-channel FET also being held at ground potential. Certain obvious variations of the circuit are possible. For example, the function of the first and second N-channel FETs may be reversed. In addition, the second P-channel FET functions as a resistor, and may be replaced with any device which functions as a resistor.
摘要翻译： 公开了一种新的反相输出驱动器电路，其通过电路的上拉场效应晶体管的漏极减少到衬底中的电子注入。 这是通过添加允许上拉晶体管的栅极电压跟踪源极电压的附加电路来实现的。 输出电路使用具有通过第一P沟道FET耦合到VCC的输出节点（以下称为中间节点）的逆变器，并且分别通过第一和第二串联耦合的N沟道FET接地。 P沟道FET和第一N沟道FET的栅极耦合到输入节点并由输入节点控制。 逆变器输出节点控制第三N沟道FET的栅极，最终的输出节点通过该栅极耦合到VCC。 中间节点通过第四N沟道FET耦合到最终输出节点，第四N沟道FET的栅极保持在地电位。 第二N沟道FET的栅极通过第二P沟道FET耦合到VCC，并通过具有比第二P沟道FET大得多的驱动的第五N沟道FET耦合到最终输出节点; 第二P沟道FET和第五N沟道FET两者的栅极也保持接地电位。 电路的某些明显变化是可能的。 例如，第一和第二N沟道FET的功能可以颠倒。 此外，第二P沟道FET用作电阻器，并且可以用用作电阻器的任何器件替代。
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公开(公告)号：US6124163A
公开(公告)日：2000-09-26
申请号：US459131
申请日：1999-12-10
IPC分类号： H01L21/02 , H01L27/06 , H01L27/105 , H01L29/92 , H01L21/283
CPC分类号： H01L27/105 , H01L27/0623 , H01L27/0629 , H01L28/40
摘要： A multilayer decoupling capacitor structure is disclosed, having a first decoupling capacitor with one electrode formed in a conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. A third bifurcated conductive layer disposed above the second electrode in conjunction with a fourth conductive layer above the third layer form a second and third decoupling capacitor. The first decoupling capacitor serves to decouple circuitry associated with dynamic random access memory cells, while the second and third decoupling capacitors provide decoupling for further circuitry.
摘要翻译： 公开了一种多层去耦电容器结构，其具有在导电掺杂硅衬底中形成的一个电极的第一去耦电容器和由导电掺杂多晶硅制成的第二电极。 配置在第二电极上方的第三分支导电层与第三层上方的第四导电层结合形成第二和第三去耦电容器。 第一去耦电容器用于去耦合与动态随机存取存储器单元相关的电路，而第二和第三去耦电容器为进一步的电路提供去耦。
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公开(公告)号：US5739576A
公开(公告)日：1998-04-14
申请号：US539855
申请日：1995-10-06
IPC分类号： H01L21/02 , H01L27/06 , H01L27/105 , H01L29/92 , H01L29/00
CPC分类号： H01L27/105 , H01L27/0623 , H01L27/0629 , H01L28/40
摘要： A multilayer decoupling capacitor structure is disclosed, having a first decoupling capacitor with one electrode formed in a conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. A third bifurcated conductive layer disposed above the second electrode in conjunction with a fourth conductive layer above the third layer form a second and third decoupling capacitor. The first decoupling capacitor serves to decouple circuitry associated with dynamic random access memory cells, while the second and third decoupling capacitors provide decoupling for further circuitry.
摘要翻译： 公开了一种多层去耦电容器结构，其具有在导电掺杂硅衬底中形成的一个电极的第一去耦电容器和由导电掺杂多晶硅制成的第二电极。 配置在第二电极上方的第三分支导电层与第三层上方的第四导电层结合形成第二和第三去耦电容器。 第一去耦电容器用于去耦合与动态随机存取存储器单元相关的电路，而第二和第三去耦电容器为进一步的电路提供去耦。
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8.发明授权Inverting output driver circuit for reducing electron injection into the substrate 失效用于减少电子注入基板的反相输出驱动电路
公开(公告)号：US5347179A
公开(公告)日：1994-09-13
申请号：US48158
申请日：1993-04-15
IPC分类号： H03K17/16 , H03K17/08 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0948 , H03K19/20
CPC分类号： H03K19/00361 , H03K19/00315
摘要： A new inverting output driver circuit is disclosed that reduces electron injection into the substrate by the drain of the circuit's pull-up field effect transistor. This is accomplished by adding additional circuitry that allows the gate voltage of the pull-up transistor to track the source voltage. The output circuit makes use of an inverter having an output node (hereinafter the intermediate node) coupled to V.sub.CC through a first P-channel FET, and to ground through first and second series coupled N-channel FETs, respectively. The gates of the P-channel FET and the first N-channel FET are coupled to and controlled by an input node. The inverter output node controls the gate of third N-channel FET, through which a final output node is coupled to V.sub.CC. The intermediate node is coupled to the final output node through a fourth N-channel FET, the gate of which is held at ground potential. The gate of the second N-channel FET is coupled to V.sub.CC through a second P-channel FET and to the final output node through a fifth N-channel FET which has much greater drive than the second P-channel FET; the gates of both the second P-channel FET and the fifth N-channel FET also being held at ground potential. Certain obvious variations of the circuit are possible. For example, the function of the first and second N-channel FETs may be reversed. In addition, the second P-channel FET functions as a resistor, and may be replaced with any device which functions as a resistor.
摘要翻译： 公开了一种新的反相输出驱动器电路，其通过电路的上拉场效应晶体管的漏极减少到衬底中的电子注入。 这是通过添加允许上拉晶体管的栅极电压跟踪源极电压的附加电路来实现的。 输出电路使用具有通过第一P沟道FET耦合到VCC的输出节点（以下称为中间节点）的逆变器，并且分别通过第一和第二串联耦合的N沟道FET接地。 P沟道FET和第一N沟道FET的栅极耦合到输入节点并由输入节点控制。 逆变器输出节点控制第三N沟道FET的栅极，最终的输出节点通过该栅极耦合到VCC。 中间节点通过第四N沟道FET耦合到最终输出节点，第四N沟道FET的栅极保持在地电位。 第二N沟道FET的栅极通过第二P沟道FET耦合到VCC，并通过具有比第二P沟道FET大得多的驱动的第五N沟道FET耦合到最终输出节点; 第二P沟道FET和第五N沟道FET两者的栅极也保持接地电位。 电路的某些明显变化是可能的。 例如，第一和第二N沟道FET的功能可以颠倒。 此外，第二P沟道FET用作电阻器，并且可以用用作电阻器的任何器件替代。
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9.发明授权System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices 有权用于在动态随机存取存储器件的扩展刷新周期期间降低功耗的系统和方法公开(公告)号：US07995415B2
公开(公告)日：2011-08-09
申请号：US12082579
申请日：2008-04-11
申请人： Stephen L. Casper
发明人： Stephen L. Casper
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1006 , G11C7/1078 , G11C11/40615 , G11C11/4074 , G11C11/4096 , G11C2211/4067 , G11C2211/4068
摘要： A dynamic random access memory (“DRAM”) device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh mode and in the static refresh mode when memory cells are being refreshed. In between refresh bursts in the static refresh mode, the cell plate voltage selector couples a reduced voltage to the cell plate. This reduces the voltage reduces the voltage across diode junctions formed between the source/drain of respective access transistor and the substrate. The reduced voltage reduces the discharge current flowing from memory cells capacitors, thereby allowing a reduction in the required refresh rate and a consequential reduction in power consumption.
摘要翻译： 动态随机存取存储器（“DRAM”）设备可以在正常刷新模式或静态刷新模式（诸如自刷新模式）中操作。 电池板电压选择器将正常刷新模式下的电源电压的一半电压与DRAM阵列的单元板耦合，并且当刷新存储器单元时，静态刷新模式。 在静态刷新模式下的刷新突发之间，单元板电压选择器将降低的电压耦合到单元板。 这降低了形成在各个存取晶体管的源极/漏极与衬底之间的二极管结上的电压。 降低的电压降低了从存储单元电容器流出的放电电流，从而允许减少所需的刷新率并因此降低功耗。
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公开(公告)号：US06922368B2
公开(公告)日：2005-07-26
申请号：US10820406
申请日：2004-04-08
申请人： Stephen L. Casper
发明人： Stephen L. Casper
IPC分类号： F01D5/30 , F01D9/04 , G11C7/20 , G11C11/4072 , G11C7/00
CPC分类号： G11C11/4072 , G11C7/20
摘要： A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.
摘要翻译： 在初始施加电力时减少启用动态随机存取存储器（DRAM）的时间的方法和装置包括在初始上电时产生内部RAS信号以产生内部电压。 在短时间延迟结束后，内部RAS脉冲被置位。 在内部RAS脉冲被置位之后，数字线对上的电压用读出放大器放大。 然后，数字线对上的放大电压用平衡电路平衡。 平衡电压也通过平衡电路耦合以对存储单元电容器的公共板充电。
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