公开(公告)号：US20080263384A1

公开(公告)日：2008-10-23

申请号：US11738841

申请日：2007-04-23

申请人： Steven C. Miller ,  Naresh Patel

发明人： Steven C. Miller ,  Naresh Patel

IPC分类号： G06F1/04

CPC分类号： G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  G06F9/3869 ,  G06F9/3891 ,  Y02D10/126

摘要： A system and method for prioritization of clock rates in a multi-core processor is provided. Instruction arrival rates are measured during a time interval Ti−1 to Ti by a monitoring module either internal to the processor or operatively interconnected with the processor. Using the measured instruction arrival rates, the monitoring module calculates an optimal instruction arrival rate for each core of the processor. For processors that support continuous frequency changes for cores, each core is then set to an optimal service rate. For processors that only support a discrete set of arrival rates, the optimal rates are mapped to a closest supported rate and the cores are set to the closest supported rate. This procedure is then repeated for each time interval.

摘要翻译： 提供了一种用于在多核处理器中优先化时钟速率的系统和方法。 指令到达速率在处理器内部或与处理器可操作地互连的监视模块在时间间隔T i-1至T i i中被测量。 使用测量的指令到达率，监视模块为处理器的每个核心计算最佳指令到达速率。 对于支持内核连续频率更改的处理器，每个核心然后设置为最佳服务速率。 对于仅支持离散到达率集合的处理器，最优速率被映射到最接近的支持速率，并且核心被设置为最接近的支持速率。 然后每个时间间隔重复该过程。

公开(公告)号：US08015427B2

公开(公告)日：2011-09-06

申请号：US11738841

申请日：2007-04-23

申请人： Steven C. Miller ,  Naresh Patel

发明人： Steven C. Miller ,  Naresh Patel

IPC分类号： G06F5/06 ,  G06F1/00 ,  G06F9/30

CPC分类号： G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  G06F9/3869 ,  G06F9/3891 ,  Y02D10/126

摘要： A system and method for prioritization of clock rates in a multi-core processor is provided. Instruction arrival rates are measured during a time interval Ti−1 to Ti by a monitoring module either internal to the processor or operatively interconnected with the processor. Using the measured instruction arrival rates, the monitoring module calculates an optimal instruction arrival rate for each core of the processor. For processors that support continuous frequency changes for cores, each core is then set to an optimal service rate. For processors that only support a discrete set of arrival rates, the optimal rates are mapped to a closest supported rate and the cores are set to the closest supported rate. This procedure is then repeated for each time interval.

摘要翻译： 提供了一种用于在多核处理器中优先化时钟速率的系统和方法。 指令到达率在时间间隔Ti-1至Ti期间由处理器内部或与处理器可操作地互连的监视模块测量。 使用测量的指令到达率，监视模块为处理器的每个核心计算最佳指令到达速率。 对于支持内核连续频率更改的处理器，每个核心然后设置为最佳服务速率。 对于仅支持离散到达率集合的处理器，最优速率被映射到最接近的支持速率，并且核心被设置为最接近的支持速率。 然后每个时间间隔重复该过程。

公开(公告)号：US09107630B2

公开(公告)日：2015-08-18

申请号：US12762181

申请日：2010-04-16

申请人： Heidi D. Zhang ,  Robert F. Lawrence ,  Gilbert M. Lima ,  Steven C. Miller ,  Anne L. Hall

发明人： Heidi D. Zhang ,  Robert F. Lawrence ,  Gilbert M. Lima ,  Steven C. Miller ,  Anne L. Hall

IPC分类号： A61B8/08 ,  A61B8/00 ,  G01S7/52 ,  G01S15/89

CPC分类号： A61B8/4218 ,  A61B6/502 ,  A61B8/0825 ,  A61B8/42 ,  A61B8/4416 ,  G01S7/52079 ,  G01S15/8915 ,  G01S15/8938 ,  G01S15/899

摘要： An ultrasound breast imaging assembly includes first and second compression plates angled with respect to one another, a breast compression area defined between the first and second compression plates, at least one pivot assembly, and an ultrasound probe. The pivot assembly allows relative motion between the first and second compression plates. The ultrasound probe, which is configured to translate over one of the first and second compression plates, includes an active matrix array (AMA) positioned on one of the first and second compression plates.

摘要翻译： 超声乳房成像组件包括相对于彼此成角度的第一和第二压缩板，限定在第一和第二压缩板之间的乳房压缩区域，至少一个枢轴组件和超声波探头。 枢轴组件允许第一和第二压缩板之间的相对运动。 配置成平移第一和第二压缩板中的一个的超声波探头包括位于第一和第二压缩板之一上的有源矩阵阵列（AMA）。

公开(公告)号：US20110113153A1

公开(公告)日：2011-05-12

申请号：US13008635

申请日：2011-01-18

申请人： Steven C. Miller ,  Thomas Edward McGee ,  Bruce Alan Strangfeld

发明人： Steven C. Miller ,  Thomas Edward McGee ,  Bruce Alan Strangfeld

IPC分类号： G06F15/16

CPC分类号： H03M13/05 ,  G06F13/4217 ,  G06F15/16

摘要： A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, if a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.

摘要翻译： 用于传送数据的系统和方法包括确定在计算机模块处是否已经接收到交易请求信用的能力，指示可以发送交易请求消息的至少一部分的交易请求信用。 系统和方法还包括确定是否要发送交易请求消息的能力，是否可以发送交易请求消息的至少一部分，并且如果可以发送交易请求消息的至少一部分 被发送。

公开(公告)号：US07925839B1

公开(公告)日：2011-04-12

申请号：US12168689

申请日：2008-07-07

申请人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

发明人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

IPC分类号： G06F12/00

CPC分类号： G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831

摘要： A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

摘要翻译： 处理器可以以多个操作状态中的一个操作。 在正常操作状态下，处理器不涉及存储器事务。 在接收到访问存储器位置的事务指令时，处理器转换到事务操作状态。 在事务操作状态中，处理器执行对高速缓存线的更改和与存储器位置相关联的数据。 在事务操作状态下，数据和高速缓存行的任何更改对于计算系统中的其他处理器是不可见的。 响应于接收到提交指令，处理器进入提交操作状态时，这些更改变为可见。 更改变为可见后，处理器返回到正常运行状态。 如果在接收提交指令之前发生中止事件，则处理器转换到中止操作状态，其中对数据和高速缓存行的任何改变被丢弃。

公开(公告)号：US20080206888A1

公开(公告)日：2008-08-28

申请号：US12069724

申请日：2008-02-11

申请人： Steven C. Miller ,  Paul B. Comita ,  Christopher B. Shumate ,  Evan F. Cromwell

发明人： Steven C. Miller ,  Paul B. Comita ,  Christopher B. Shumate ,  Evan F. Cromwell

IPC分类号： G01N33/566 ,  G01N21/76

CPC分类号： G01N33/542 ,  G01N2500/00

摘要： Methods and apparatus are described for detecting specific binding between first and second chemical entities. The first chemical entity in association with a first fluorophore is immobilized. The second chemical entity is allowed to bind with the immobilized first chemical entity. The second chemical entity is or becomes coupled to a second fluorophore, which forms a FRET pair with the first fluorophore. The bound chemical entities are exposed to radiation at an excitation frequency for either the first or the second fluorophore, and polarization anisotropy of a FRET fluorescent signal from the bound chemical entities is measured to detect specific binding between the first and second chemical entities. Techniques are also disclosed for detecting whether a FRET interaction is occurring between a first chemical entity including a donor fluorophore and a second chemical entity including an acceptor fluorophore, using simultaneous anisotropy measurements at the wavelengths of the donor and acceptor fluorophores.

摘要翻译： 描述了用于检测第一和第二化学实体之间的特异性结合的方法和装置。 与第一荧光团相关联的第一化学实体被固定化。 允许第二化学实体与固定化的第一化学实体结合。 第二化学实体是或连接到与第一荧光团形成FRET对的第二荧光团。 结合的化学实体以第一或第二荧光团的激发频率暴露于辐射，并且测量来自结合的化学实体的FRET荧光信号的偏振各向异性以检测第一和第二化学实体之间的特异性结合。 还公开了用于检测在包括供体荧光团的第一化学实体和包括受体荧光团的第二化学实体之间是否发生FRET相互作用的技术，其使用在供体和受体荧光团的波长处的同时各向异性测量。

公开(公告)号：US07141378B2

公开(公告)日：2006-11-28

申请号：US11173814

申请日：2005-07-01

申请人： Steven C. Miller ,  Paul B. Comita ,  Evan F. Cromwell ,  Christopher B. Shumate

发明人： Steven C. Miller ,  Paul B. Comita ,  Evan F. Cromwell ,  Christopher B. Shumate

IPC分类号： C12Q1/68 ,  G01N33/53

CPC分类号： G01N33/582 ,  B82Y5/00 ,  B82Y10/00 ,  C12Q1/6816 ,  G01N21/6408 ,  G01N21/6428 ,  G01N21/6445 ,  G01N2021/6419 ,  G01N2021/6421 ,  G01N2021/6432 ,  G01N2021/6441 ,  G01N2021/6478 ,  G01N2021/6484 ,  G01N2201/067 ,  G01N2201/0697 ,  G01N2201/0833 ,  C12Q2563/107 ,  C12Q2561/119

摘要： Methods, apparatus, and system, implementing and using techniques for detecting a presence of one or more target analytes in particular regions of interest of one or more samples. One or more samples including objects and one or more target analytes are provided. Some of the target analytes are labeled with a fluorophore and are bound to some of the objects in the samples. The samples are illuminated with fluorescence inducing light and fluorescent light is collected from one or more regions of the one or more samples. At least one anisotropy measurement of the samples is performed to identify regions of interest where one or more target analytes are bound to the objects. The collected fluorescent light from the regions of interest is analyzed to determine a presence of target analytes that are bound to the objects in the one or more samples.

摘要翻译： 方法，装置和系统，实施和使用用于检测一个或多个样品的特定感兴趣区域中一种或多种目标分析物的存在的技术。 提供了一个或多个样品，包括物体和一种或多种目标分析物。 一些目标分析物用荧光团标记，并且与样品中的某些对象结合。 用荧光诱导光照射样品，并从一个或多个样品的一个或多个区域采集荧光。 进行样品的至少一个各向异性测量以识别一个或多个目标分析物与物体结合的感兴趣区域。 分析来自感兴趣区域的收集的荧光以确定与一个或多个样品中的物体结合的目标分析物的存在。

公开(公告)号：US06795900B1

公开(公告)日：2004-09-21

申请号：US09910363

申请日：2001-07-20

申请人： Steven C. Miller ,  Jeffrey S. Kuskin ,  William A. Huffman ,  Gregory M. Thorson

发明人： Steven C. Miller ,  Jeffrey S. Kuskin ,  William A. Huffman ,  Gregory M. Thorson

IPC分类号： G06F1200

CPC分类号： G06F12/0817 ,  G06F2212/2542 ,  G06F2212/621

摘要： A multiprocessor system and method includes a processing sub-system including a plurality of processors in a processor memory system. A network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces each operable to couple a peripheral device to the multiprocessor system. The I/O interfaces each include a local memory operable to store exclusive read-only copies of data from the processor memory system for use by a corresponding peripheral device.

摘要翻译： 多处理器系统和方法包括在处理器存储器系统中包括多个处理器的处理子系统。 网络可操作以将处理子系统耦合到输入/输出（I / O）子系统。 I / O子系统包括多个I / O接口，每个I / O接口可操作以将外围设备耦合到多处理器系统。 I / O接口各自包括本地存储器，其可操作以存储来自处理器存储器系统的数据的专用只读副本以供对应的外围设备使用。

公开(公告)号：US06443897B1

公开(公告)日：2002-09-03

申请号：US09750869

申请日：2000-12-28

申请人： David T. Dubberstein ,  Steven C. Miller

发明人： David T. Dubberstein ,  Steven C. Miller

IPC分类号： A61B0800

CPC分类号： G10K11/346

摘要： A method and an apparatus for correcting refraction delay errors on curved probes for all ranges using cordic rotation. The angle &phgr; from the normal of an element to the focus is determined as a function of the angle of cordic rotation. Then a delay error correction is indexed using this angle &phgr;. The angular correction method is efficient in that it uses the inherent property of cordic rotation to calculate the only range-dependent variable required for the correction. Thus the additional hardware required to calculate the corrections is minimal, as the remaining correction variables are vector and range independent.

摘要翻译： 一种用于校正所有范围的弯曲探针上的折射延迟误差的方法和装置，其使用线性旋转。 从元件的法线到焦点的角度phi被确定为帘线旋转角度的函数。 然后使用该角度phi对延迟误差校正进行索引。 角度校正方法是有效的，因为它使用线性旋转的固有属性来计算校正所需的唯一的范围因变量。 因此，计算校正所需的附加硬件是最小的，因为剩余的校正变量是向量和范围无关的。

公开(公告)号：US06282195B1

公开(公告)日：2001-08-28

申请号：US08780785

申请日：1997-01-09

申请人： Steven C. Miller ,  James E. Tornes

发明人： Steven C. Miller ,  James E. Tornes

IPC分类号： H04L1256

CPC分类号： H04L49/253 ,  H04L49/30

摘要： A switched router for transmitting packetized data concurrently between a plurality of devices coupled to the switched router. The devices are coupled to the I/O ports of the switched router. The switched router is then programmed to route packets of data from various source ports to several destination ports. Different packets may be transmitted concurrently through the switched router. The packets are comprised of a command word containing information corresponding to packet routing, data format, size, and transaction identification. Furthermore, the command word may include a destination identification number for routing the packet to a destination device, a source identification number used by a destination device to send back responses, a transaction number to tag requests that require a response, and a packet type value indicating a particular type of packet. In addition, there may be bits within a packet used to indicate a coherent transaction, guarantee bandwidth, an error during transmission, or a sync barrier for write ordering. Other types of packets may include a fetch and operation packet with increment by one, a fetch and operation packet with decrement by one, a fetch and operation packet with clear, a store and operation packet with increment by one, a store and operation packet with decrement by one, a store and operation packet with a logical OR, and a store and operation packet with a logical AND.

摘要翻译： 一种用于在耦合到所述交换路由器的多个设备之间并发地发送分组化数据的交换路由器。 这些设备耦合到交换路由器的I / O端口。 然后将交换路由器编程为将数据包从各种源端口路由到多个目的端口。 可以通过交换路由器同时发送不同的分组。 分组由包含对应于分组路由，数据格式，大小和事务标识的信息的命令字组成。 此外，命令字可以包括用于将分组路由到目的地设备的目的地标识号，目的地设备用于发送回应用的源标识号，用于标记需要响应的请求的事务号，以及分组类型值 指示特定类型的数据包。 此外，在用于指示相干事务，保证带宽，传输期间的错误或用于写入顺序的同步屏障中的分组中可能存在位。 其他类型的分组可以包括递增1的获取和操作分组，递减1的获取和操作分组，具有清除的获取和操作分组，具有递增1的存储和操作分组，具有递增1的存储和操作分组， 递减1，具有逻辑OR的存储和操作分组以及具有逻辑AND的存储和操作分组。