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    Forming CMOS with close proximity stressors
    7.
    发明授权
    Forming CMOS with close proximity stressors 有权
    形成具有接近应力的CMOS

    公开(公告)号：US09041119B2

    公开(公告)日：2015-05-26

    申请号：US13465159

    申请日：2012-05-07

    申请人： Desmond J. Donegan, Jr. ,  Abhishek Dube ,  Steven Jones ,  Jophy S. Koshy ,  Viorel Ontalus

    发明人： Desmond J. Donegan, Jr. ,  Abhishek Dube ,  Steven Jones ,  Jophy S. Koshy ,  Viorel Ontalus

    IPC分类号： H01L29/02 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/66636

    摘要： A method of forming transistors with close proximity stressors to channel regions of the transistors is provided. The method includes forming a first transistor, in a first region of a substrate, having a gate stack on top of the first region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the first region including a source and drain region of the first transistor; forming a second transistor, in a second region of the substrate, having a gate stack on top of the second region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the second region including a source and drain region of the second transistor; covering the first transistor with a photo-resist mask without covering the second transistor; creating recesses in the source and drain regions of the second transistor; and forming stressors in the recesses.

    摘要翻译： 提供了一种形成具有接近应力的晶体管到晶体管的沟道区域的方法。 该方法包括在衬底的第一区域中形成第一晶体管，在衬底的第一区域的顶部上具有栅极叠层，以及邻近栅堆叠的侧壁的一组间隔物，第一区域包括源极和漏极 第一晶体管的区域; 在所述衬底的第二区域中形成第二晶体管，在所述衬底的所述第二区域的顶部上具有栅极叠层，以及邻近所述栅极叠层的侧壁的一组间隔区，所述第二区域包括所述栅极叠层的源极和漏极区域 第二晶体管; 用光致抗蚀剂掩模覆盖第一晶体管而不覆盖第二晶体管; 在所述第二晶体管的源极和漏极区域中产生凹陷; 并在凹槽中形成应力源。