公开(公告)号：US20050148147A1

公开(公告)日：2005-07-07

申请号：US10750054

申请日：2003-12-30

Applicant: Steven Keating ,  Chris Auth

Inventor： Steven Keating ,  Chris Auth

IPC: H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/336 ,  H01L29/165 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/165

Abstract: Methods of forming an amorphous etch stop layer by implanting a substrate with an element that is electrically neutral within the substrate are described. The use of elements that are electrically neutral within the substrate prevents electrical interference by the elements if they diffuse to other areas within the substrate. The amorphous etch stop layer may be used as a hard mask in the fabrication of transistors or other devices such as a cantilever.

Abstract translation: 描述通过在衬底内注入具有电中性元素的衬底来形成非晶态蚀刻停止层的方法。 在衬底内使用电气中性的元件如果它们扩散到衬底内的其它区域，则防止元件的电干扰。 非晶蚀刻停止层可用作制造晶体管或诸如悬臂的其它器件的硬掩模。

公开(公告)号：US07045407B2

公开(公告)日：2006-05-16

申请号：US10750054

申请日：2003-12-30

Applicant: Steven Keating ,  Chris Auth

Inventor： Steven Keating ,  Chris Auth

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/165

Abstract: Methods of forming an amorphous etch stop layer by implanting a substrate with an element that is electrically neutral within the substrate are described. The use of elements that are electrically neutral within the substrate prevents electrical interference by the elements if they diffuse to other areas within the substrate. The amorphous etch stop layer may be used as a hard mask in the fabrication of transistors or other devices such as a cantilever.

Abstract translation: 描述通过在衬底内注入具有电中性元素的衬底来形成非晶态蚀刻停止层的方法。 在衬底内使用电气中性的元件如果它们扩散到衬底内的其它区域，则防止元件的电干扰。 非晶蚀刻停止层可用作制造晶体管或诸如悬臂的其它器件的硬掩模。

公开(公告)号：US07335959B2

公开(公告)日：2008-02-26

申请号：US11031843

申请日：2005-01-06

Applicant: Giuseppe Curello ,  Bernhard Sell ,  Sunit Tyagi ,  Chris Auth

Inventor： Giuseppe Curello ,  Bernhard Sell ,  Sunit Tyagi ,  Chris Auth

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842

Abstract: Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.

Abstract translation: 本发明的实施例提供了具有阶梯式源极和漏极区域的晶体管。 台阶区域可以在通道区域中提供显着的应变，同时最小化电流泄漏。 可以通过在基板中形成两个凹槽来形成阶梯状区域，以形成阶梯状凹陷，并且在凹部中形成源极/漏极区域。

公开(公告)号：US08766372B2

公开(公告)日：2014-07-01

申请号：US13569150

申请日：2012-08-07

Applicant: Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

Inventor： Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

IPC: H01L21/02

CPC classification number: H01L29/41725 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

Abstract translation: 制造半导体器件的第一接触的方法，其基本上包括提供形成在衬底上的半导体器件。 基板还包括导电表面。 介电层形成在衬底上并具有暴露导电表面的开口。 开口延伸半导体器件的整个长度，从设备的整个长度的一部分延伸到器件的相邻的场上，或其组合。 在开口内形成阻挡层。 含铜材料填充开口以形成与半导体器件的第一接触。

公开(公告)号：US20050230760A1

公开(公告)日：2005-10-20

申请号：US11152266

申请日：2005-06-13

Applicant: Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

Inventor： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/76

CPC classification number: H01L29/66636 ,  H01L21/823418

Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

Abstract translation: 描述形成微电子结构的方法和相关装置。 那些方法包括提供一种衬底，其包括具有源极和漏极凹部的较高有源面积密度的区域和包括源极和漏极凹陷的较低有源面积密度的区域，其中较低有源面积密度的区域还包括虚设凹槽，并且选择性地沉积 源极，漏极和虚拟凹槽中的硅合金层，以增强硅合金沉积的选择性和均匀性。

公开(公告)号：US20120299069A1

公开(公告)日：2012-11-29

申请号：US13569150

申请日：2012-08-07

Applicant: Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

Inventor： Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

IPC: H01L23/48 ,  H01L29/78

CPC classification number: H01L29/41725 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

Abstract translation: 制造半导体器件的第一接触的方法，其基本上包括提供形成在衬底上的半导体器件。 基板还包括导电表面。 介电层形成在衬底上并具有暴露导电表面的开口。 开口延伸半导体器件的整个长度，从设备的整个长度的一部分延伸到器件的相邻的场上，或其组合。 在开口内形成阻挡层。 含铜材料填充开口以形成与半导体器件的第一接触。

公开(公告)号：US08258057B2

公开(公告)日：2012-09-04

申请号：US11396201

申请日：2006-05-23

Applicant: Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

Inventor： Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

IPC: H01L21/4763

CPC classification number: H01L29/41725 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

Abstract translation: 制造半导体器件的第一接触的方法，其基本上包括提供形成在衬底上的半导体器件。 基板还包括导电表面。 介电层形成在衬底上并具有暴露导电表面的开口。 开口延伸半导体器件的整个长度，从设备的整个长度的一部分延伸到器件的相邻的场上，或其组合。 在开口内形成阻挡层。 含铜材料填充开口以形成与半导体器件的第一接触。

公开(公告)号：US07045408B2

公开(公告)日：2006-05-16

申请号：US10443152

申请日：2003-05-21

Applicant: Thomas Hoffmann ,  Chris Auth ,  Mark Armstrong ,  Stephen Cea

Inventor： Thomas Hoffmann ,  Chris Auth ,  Mark Armstrong ,  Stephen Cea

IPC: H01L21/8238 ,  H01L21/84 ,  H01L21/00 ,  H01L21/461 ,  H01L21/31

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/665

Abstract: An integrated circuit is described that comprises a PMOS transistor and an NMOS transistor that are formed on a semiconductor substrate. A silicate glass layer is formed on only the PMOS transistor or the NMOS transistor; and an etch stop layer is formed on the silicate glass layer. Also described is a method for forming an integrated circuit. That method comprises forming a PMOS transistor structure and an NMOS transistor structure on a semiconductor substrate, forming a silicate glass layer on only the PMOS transistor structure or the NMOS transistor structure, and forming an etch stop layer on the silicate glass layer.

Abstract translation: 描述了一种集成电路，其包括形成在半导体衬底上的PMOS晶体管和NMOS晶体管。 仅在PMOS晶体管或NMOS晶体管上形成硅酸盐玻璃层; 并且在硅酸盐玻璃层上形成蚀刻停止层。 还描述了一种用于形成集成电路的方法。 该方法包括在半导体衬底上形成PMOS晶体管结构和NMOS晶体管结构，仅在PMOS晶体管结构或NMOS晶体管结构上形成硅酸盐玻璃层，并在硅酸盐玻璃层上形成蚀刻停止层。

公开(公告)号：US20060057809A1

公开(公告)日：2006-03-16

申请号：US11270933

申请日：2005-11-10

Applicant: Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

Inventor： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823418

Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

Abstract translation: 描述形成微电子结构的方法和相关装置。 那些方法包括提供一种衬底，其包括具有源极和漏极凹部的较高有源面积密度的区域和包括源极和漏极凹陷的较低有源面积密度的区域，其中较低有源面积密度的区域还包括虚设凹槽，并且选择性地沉积 源极，漏极和虚拟凹槽中的硅合金层，以增强硅合金沉积的选择性和均匀性。

公开(公告)号：US20140264879A1

公开(公告)日：2014-09-18

申请号：US14289581

申请日：2014-05-28

Applicant: Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

Inventor： Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

IPC: H01L29/45

CPC classification number: H01L29/41725 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

Abstract translation: 制造半导体器件的第一接触的方法，其基本上包括提供形成在衬底上的半导体器件。 基板还包括导电表面。 介电层形成在衬底上并具有暴露导电表面的开口。 开口延伸半导体器件的整个长度，从设备的整个长度的一部分延伸到器件的相邻的场上，或其组合。 在开口内形成阻挡层。 含铜材料填充开口以形成与半导体器件的第一接触。