公开(公告)号：US09287004B2

公开(公告)日：2016-03-15

申请号：US13670792

申请日：2012-11-07

申请人： Su-a Kim ,  Young-soo Sohn ,  Dae-hyun Kim

发明人： Su-a Kim ,  Young-soo Sohn ,  Dae-hyun Kim

IPC分类号： G06F11/20 ,  G06F12/00 ,  G11C29/04 ,  G11C29/00 ,  G11C7/10

CPC分类号： G11C29/04 ,  G11C7/1045 ,  G11C29/808 ,  G11C29/81 ,  G11C29/848

摘要： In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, the second memory cell group includes a plurality of second memory cells associated with a second data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. A data line selection circuit is configured to provide a data path between an input/output node and one of the first data line, the second data and the redundancy data line.

摘要翻译： 在一个实施例中，存储器件包括具有至少第一存储单元组，第二存储单元组和冗余存储单元组的存储单元阵列。 第一存储单元组包括与第一数据线相关联的多个第一存储器单元，第二存储单元组包括与第二数据线相关联的多个第二存储器单元，并且冗余存储单元组包括多个冗余存储器 与冗余数据线相关联的单元。 数据线选择电路被配置为在输入/输出节点与第一数据线，第二数据和冗余数据线之一之间提供数据路径。

公开(公告)号：US20130163355A1

公开(公告)日：2013-06-27

申请号：US13611084

申请日：2012-09-12

申请人： Jong-pil Son ,  Young-soo Sohn

发明人： Jong-pil Son ,  Young-soo Sohn

IPC分类号： G11C29/44

CPC分类号： G11C29/44 ,  G11C8/00 ,  G11C11/4087 ,  G11C16/08 ,  G11C17/16 ,  G11C29/04 ,  G11C29/787 ,  G11C29/808 ,  G11C2029/4402

摘要： A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.

公开(公告)号：US20080088350A1

公开(公告)日：2008-04-17

申请号：US11907723

申请日：2007-10-17

申请人： Young-soo Sohn

发明人： Young-soo Sohn

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K2005/00136

摘要： A duty detector may include a first amplifier and/or an integrator. The first amplifier may be configured to receive a first signal and a complementary first signal, differential-amplify the first signal and the complementary first signal, and/or output the differential-amplified first signal to an output terminal and the differential-amplified complementary first signal to a complementary output terminal. The integrator may be connected to the output terminal and the complementary output terminal of the first amplifier, configured to integrate the differential-amplified first signal and the differential-amplified complementary first signal, and/or configured to output a duty detection signal.

摘要翻译： 占空比检测器可以包括第一放大器和/或积分器。 第一放大器可以被配置为接收第一信号和互补的第一信号，差分放大第一信号和互补的第一信号，和/或将差分放大的第一信号输出到输出端和差分放大的互补的第一信号 信号到互补输出端子。 积分器可以连接到第一放大器的输出端和互补输出端，被配置为积分差分放大的第一信号和差分放大的互补第一信号，和/或被配置为输出占空比检测信号。

公开(公告)号：US09627015B2

公开(公告)日：2017-04-18

申请号：US14852890

申请日：2015-09-14

申请人： Young-soo Sohn ,  Kwang-il Park ,  Sei-jin Kim ,  Tae-young Kim

发明人： Young-soo Sohn ,  Kwang-il Park ,  Sei-jin Kim ,  Tae-young Kim

IPC分类号： G11C7/00 ,  G11C7/10

CPC分类号： G11C7/109 ,  G11C7/1063 ,  G11C2207/2272

摘要： A memory device, system, and/or method are provided for performing a page state informing function. The memory device may compare one or more row addresses received along with a command, determine the page open/close state according to a page hit or miss generated as a result of comparison, count read or write commands with respect to pages corresponding to a same row address, and determine the page open/close state according to a read or write command number generated as a result of counting. The memory device may determine a page open/close state with respect to a corresponding page based on a page hit/miss and a read or write command number and output a flag signal. The memory device may provide the page open/close state for each channel. A memory controller may establish different page open/close policies for each channel.

公开(公告)号：US09059698B2

公开(公告)日：2015-06-16

申请号：US13240635

申请日：2011-09-22

申请人： Su-yeon Doo ,  Seung-jun Bae ,  Kwang-il Park ,  Young-soo Sohn

发明人： Su-yeon Doo ,  Seung-jun Bae ,  Kwang-il Park ,  Young-soo Sohn

IPC分类号： G05F1/00 ,  H03K19/003 ,  G05F1/575

CPC分类号： H03K19/00361 ,  G05F1/575

摘要： An integrated circuit device includes an external power supply input configured to be coupled to an external power supply and a digital circuit, such as a clock signal generator circuit, that generates noise at a power supply input thereof. The device further includes a replica load circuit and a power supply circuit coupled to the external power supply input, to a power supply input of the digital circuit and to a power supply input of the replica load circuit. The power supply circuit is configured to selectively couple the external power supply node to the power supply input of the digital circuit responsive to a voltage at the power supply input of the replica load circuit. The replica load circuit may be configured to provide a load that varies responsive to a voltage at the power supply input of the digital circuit.

摘要翻译： 集成电路装置包括被配置为耦合到外部电源的外部电源输入和在其电源输入处产生噪声的数字电路，例如时钟信号发生器电路。 该装置还包括复制负载电路和耦合到外部电源输入的电源电路，数字电路的电源输入和复制负载电路的电源输入。 电源电路被配置为响应于复制负载电路的电源输入处的电压来选择性地将外部电源节点耦合到数字电路的电源输入。 复制负载电路可以被配置为提供响应于数字电路的电源输入处的电压而变化的负载。

公开(公告)号：US07579890B2

公开(公告)日：2009-08-25

申请号：US11907723

申请日：2007-10-17

申请人： Young-soo Sohn

发明人： Young-soo Sohn

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K2005/00136

摘要： A duty detector may include a first amplifier and/or an integrator. The first amplifier may be configured to receive a first signal and a complementary first signal, differential-amplify the first signal and the complementary first signal, and/or output the differential-amplified first signal to an output terminal and the differential-amplified complementary first signal to a complementary output terminal. The integrator may be connected to the output terminal and the complementary output terminal of the first amplifier, configured to integrate the differential-amplified first signal and the differential-amplified complementary first signal, and/or configured to output a duty detection signal.

摘要翻译： 占空比检测器可以包括第一放大器和/或积分器。 第一放大器可以被配置为接收第一信号和互补的第一信号，差分放大第一信号和互补的第一信号，和/或将差分放大的第一信号输出到输出端和差分放大的互补的第一信号 信号到互补输出端子。 积分器可以连接到第一放大器的输出端和互补输出端，被配置为积分差分放大的第一信号和差分放大的互补第一信号，和/或被配置为输出占空比检测信号。

公开(公告)号：US07567103B2

公开(公告)日：2009-07-28

申请号：US12007321

申请日：2008-01-09

申请人： In-soo Park ,  Young-soo Sohn

发明人： In-soo Park ,  Young-soo Sohn

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： An apparatus for detecting a lock failure and correcting a duty cycle includes a lock failure detector configured to determine whether a first internal clock signal is locked to a second internal clock signal and to output a lock failure signal in response thereto, a duty cycle correction unit configured to correct a duty cycle of an external clock signal responsive to the lock failure signal and to output the duty-cycle-corrected external clock signal as the first internal clock signal, and a delay unit configured to generate the second internal clock signal by delaying the first internal clock signal.

摘要翻译： 一种用于检测锁定失败和校正占空比的装置包括锁定故障检测器，其被配置为确定第一内部时钟信号是否被锁定到第二内部时钟信号，并且响应于此而输出锁定失败信号;占空比校正单元 配置为响应于所述锁定失败信号来校正外部时钟信号的占空比，并且输出所述占空比校正的外部时钟信号作为所述第一内部时钟信号;以及延迟单元，被配置为通过延迟来产生所述第二内部时钟信号 第一个内部时钟信号。

公开(公告)号：US07817494B2

公开(公告)日：2010-10-19

申请号：US12236978

申请日：2008-09-24

申请人： Young-soo Sohn ,  Kwang-Il Park ,  Seung-Jun Bae

发明人： Young-soo Sohn ,  Kwang-Il Park ,  Seung-Jun Bae

IPC分类号： G11C11/00

CPC分类号： G11C11/4076 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18

摘要： Integrated circuit memory devices include an internal command generator and a memory control circuit responsive to an internal command generated by the internal command generator. The internal command generator is configured to generate an internal command in response to a combination of an independent command and at least one dependent command received in sequence by the memory device. For example, the internal command generator may be configured to require the independent command to follow the at least one dependent command in the sequence when generating the internal command from the combination of the independent and dependent commands. Alternatively, the internal command generator may be configured to require the independent command to precede the at least one dependent command in the sequence before generating the internal command from the combination of the independent and dependent commands. These independent and dependent commands may be received by the memory device as respective multi-bit external command signals.

摘要翻译： 集成电路存储器件包括响应于由内部命令发生器产生的内部命令的内部命令发生器和存储器控制电路。 内部命令生成器被配置为响应于独立命令和由存储器装置依次接收的至少一个依赖命令的组合来生成内部命令。 例如，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令时，要求独立命令遵循序列中的至少一个从属命令。 或者，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令之前，要求独立命令在序列中的至少一个从属命令之前。 这些独立和依赖的命令可以被存储器装置接收为相应的多位外部命令信号。

公开(公告)号：US20090097339A1

公开(公告)日：2009-04-16

申请号：US12236978

申请日：2008-09-24

申请人： Young-soo Sohn ,  Kwang-II Park ,  Seung-Jun Bae

发明人： Young-soo Sohn ,  Kwang-II Park ,  Seung-Jun Bae

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C11/4076 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18

摘要： Integrated circuit memory devices include an internal command generator and a memory control circuit responsive to an internal command generated by the internal command generator. The internal command generator is configured to generate an internal command in response to a combination of an independent command and at least one dependent command received in sequence by the memory device. For example, the internal command generator may be configured to require the independent command to follow the at least one dependent command in the sequence when generating the internal command from the combination of the independent and dependent commands. Alternatively, the internal command generator may be configured to require the independent command to precede the at least one dependent command in the sequence before generating the internal command from the combination of the independent and dependent commands. These independent and dependent commands may be received by the memory device as respective multi-bit external command signals.

摘要翻译： 集成电路存储器件包括响应于由内部命令发生器产生的内部命令的内部命令发生器和存储器控制电路。 内部命令生成器被配置为响应于独立命令和由存储器装置依次接收的至少一个依赖命令的组合来生成内部命令。 例如，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令时，要求独立命令遵循序列中的至少一个从属命令。 或者，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令之前，要求独立命令在序列中的至少一个从属命令之前。 这些独立和依赖的命令可以被存储器装置接收为相应的多位外部命令信号。

公开(公告)号：US07358827B2

公开(公告)日：2008-04-15

申请号：US11487545

申请日：2006-07-14

申请人： Young-soo Sohn ,  Jae-hyung Lee

发明人： Young-soo Sohn ,  Jae-hyung Lee

IPC分类号： H03L7/093

CPC分类号： H03L7/107 ,  H03L7/081 ,  H03L7/0893 ,  H03L7/0895 ,  H03L7/093

摘要： A process-insensitive self-biasing PLL circuit and self-biasing method thereof prevent deterioration of loop stability even when there is a fabrication process variation. The self-biasing PLL circuit includes a phase frequency detector, a main charge pump circuit, an auxiliary charge pump circuit, a first operational amplifier, a second operational amplifier, a voltage-controlled oscillator, a divider, and a bias circuit. In the self-biasing PLL circuit, the first operational amplifier amplifies the voltage of a loop filter capacitor and the second operational amplifier serving as a regulator amplifies the output voltage of the first operational amplifier. The output voltage of the second operational amplifier is used as a control voltage of the voltage-controlled oscillator. Particularly, the bias circuit generates a first bias current using an NMOS transistor, generates a second bias current using a PMOS transistor, and sums up the first and second bias currents to generate a third bias current in response to the output voltage of the second operational amplifier. The first bias current is provided to the main charge pump circuit and the auxiliary charge pump circuit as their bias currents, and the third bias current is provided to the first operational amplifier as its bias current.

摘要翻译： 不敏感的自偏置PLL电路及其自偏置方法即使在存在制造工艺变化时也防止环路稳定性的恶化。 自偏置PLL电路包括相位频率检测器，主电荷泵电路，辅助电荷泵电路，第一运算放大器，第二运算放大器，压控振荡器，分频器和偏置电路。 在自偏置PLL电路中，第一运算放大器放大环路滤波电容器的电压，并且用作调节器的第二运算放大器放大第一运算放大器的输出电压。 第二运算放大器的输出电压用作压控振荡器的控制电压。 特别地，偏置电路使用NMOS晶体管产生第一偏置电流，使用PMOS晶体管产生第二偏置电流，并且对第一和第二偏置电流求和以响应于第二操作的输出电压产生第三偏置电流 放大器 将第一偏置电流作为其偏置电流提供给主电荷泵电路和辅助电荷泵电路，并且将第三偏置电流作为其偏置电流提供给第一运算放大器。