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    Semiconductor memory device and system having redundancy cells
    1.
    发明授权
    Semiconductor memory device and system having redundancy cells 有权
    具有冗余单元的半导体存储器件和系统

    公开(公告)号：US09287004B2

    公开(公告)日：2016-03-15

    申请号：US13670792

    申请日：2012-11-07

    申请人： Su-a Kim ,  Young-soo Sohn ,  Dae-hyun Kim

    发明人： Su-a Kim ,  Young-soo Sohn ,  Dae-hyun Kim

    IPC分类号： G06F11/20 ,  G06F12/00 ,  G11C29/04 ,  G11C29/00 ,  G11C7/10

    CPC分类号： G11C29/04 ,  G11C7/1045 ,  G11C29/808 ,  G11C29/81 ,  G11C29/848

    摘要： In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, the second memory cell group includes a plurality of second memory cells associated with a second data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. A data line selection circuit is configured to provide a data path between an input/output node and one of the first data line, the second data and the redundancy data line.

    摘要翻译： 在一个实施例中，存储器件包括具有至少第一存储单元组，第二存储单元组和冗余存储单元组的存储单元阵列。 第一存储单元组包括与第一数据线相关联的多个第一存储器单元，第二存储单元组包括与第二数据线相关联的多个第二存储器单元，并且冗余存储单元组包括多个冗余存储器 与冗余数据线相关联的单元。 数据线选择电路被配置为在输入/输出节点与第一数据线，第二数据和冗余数据线之一之间提供数据路径。

    Trap charge equalizing method and threshold voltage distribution reducing method
    2.
    发明授权
    Trap charge equalizing method and threshold voltage distribution reducing method 失效
    陷阱电荷均衡方法和阈值电压分布降低方法

    公开(公告)号：US08058187B2

    公开(公告)日：2011-11-15

    申请号：US12652052

    申请日：2010-01-05

    申请人： Ki-whan Song ,  Su-a Kim

    发明人： Ki-whan Song ,  Su-a Kim

    IPC分类号： H01L21/30

    CPC分类号： H01L27/11575 ,  G11C11/5671 ,  H01L27/10876 ,  H01L29/66833 ,  H01L29/792

    摘要： A method reduces a threshold voltage distribution in transistors of a semiconductor memory device, where each transistor includes a nitride liner. The method includes injecting electrons into a charge trap inside and outside the nitride liner of the transistors, and partially removing the electrons injected into the charge trap inside and outside the nitride liner to equalize trapped charges in the transistors.

    摘要翻译： 一种方法降低半导体存储器件的晶体管中的阈值电压分布，其中每个晶体管包括氮化物衬垫。 该方法包括将电子注入到晶体管的氮化物衬垫内部和外部的电荷陷阱中，并且部分地去除注入氮化物衬垫内部和外部的电荷阱的电子，以平衡晶体管中的俘获电荷。

    TRAP CHARGE EQUALIZING METHOD AND THRESHOLD VOLTAGE DISTRIBUTION REDUCING METHOD
    3.
    发明申请
    TRAP CHARGE EQUALIZING METHOD AND THRESHOLD VOLTAGE DISTRIBUTION REDUCING METHOD 失效
    TRAP充电均衡方法和阈值电压分配减少方法

    公开(公告)号：US20100173503A1

    公开(公告)日：2010-07-08

    申请号：US12652052

    申请日：2010-01-05

    申请人： Ki-whan Song ,  Su-a Kim

    发明人： Ki-whan Song ,  Su-a Kim

    IPC分类号： H01L21/30

    CPC分类号： H01L27/11575 ,  G11C11/5671 ,  H01L27/10876 ,  H01L29/66833 ,  H01L29/792

    摘要： A method reduces a threshold voltage distribution in transistors of a semiconductor memory device, where each transistor includes a nitride liner. The method includes injecting electrons into a charge trap inside and outside the nitride liner of the transistors, and partially removing the electrons injected into the charge trap inside and outside the nitride liner to equalize trapped charges in the transistors.

    摘要翻译： 一种方法降低半导体存储器件的晶体管中的阈值电压分布，其中每个晶体管包括氮化物衬垫。 该方法包括将电子注入到晶体管的氮化物衬垫内部和外部的电荷陷阱中，并且部分地去除注入氮化物衬垫内部和外部的电荷阱的电子，以平衡晶体管中的俘获电荷。

    Semiconductor memory device having column redundancy scheme to improve redundancy efficiency
    4.
    发明授权
    Semiconductor memory device having column redundancy scheme to improve redundancy efficiency 有权
    具有列冗余方案以提高冗余效率的半导体存储器件

    公开(公告)号：US06414896B1

    公开(公告)日：2002-07-02

    申请号：US09905376

    申请日：2001-07-13

    申请人： Su-a Kim ,  Byung-sick Moon

    发明人： Su-a Kim ,  Byung-sick Moon

    IPC分类号： G11C800

    CPC分类号： G11C29/808 ,  G11C29/846

    摘要： A semiconductor memory device having a column redundancy scheme for improving redundancy efficiency includes sub memory blocks, a redundancy memory block, global data input output lines respectively associated with the sub memory blocks, a redundancy global data input output line and switches. Each of the sub memory blocks has a plurality of memory cells. The redundancy memory block has a plurality of redundancy memory cells. The data of selected memory cells of a sub memory block are transmitted to a corresponding global data input output line. The data of selected redundancy memory cells of the redundancy memory block are transmitted to the redundancy global data input output line. A switch switches the global data input output line to the redundancy global data input output line if a memory cell connected to the global data input output line is defective.

    摘要翻译： 具有用于提高冗余效率的列冗余方案的半导体存储器件包括子存储块，冗余存储块，分别与子存储块相关联的全局数据输入输出线，冗余全局数据输入输出线和开关。 每个子存储块具有多个存储单元。 冗余存储块具有多个冗余存储单元。 子存储器块的所选存储单元的数据被发送到相应的全局数据输入输出线。 冗余存储器块的所选择的冗余存储单元的数据被发送到冗余全局数据输入输出线。 如果连接到全局数据输入输出线的存储单元发生故障，则A开关将全局数据输入输出线切换到冗余全局数据输入输出线。

    Memory device capable of quickly repairing fail cell
    5.
    发明授权
    Memory device capable of quickly repairing fail cell 有权

    公开(公告)号：US10235258B2

    公开(公告)日：2019-03-19

    申请号：US14683705

    申请日：2015-04-10

    申请人： Jong-pil Son ,  Chul-woo Park ,  Su-a Kim

    发明人： Jong-pil Son ,  Chul-woo Park ,  Su-a Kim

    IPC分类号： G06F11/20 ,  G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G06F11/10 ,  G11C29/04

    摘要： The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.

    Semiconductor memory device having data input/output line shared by a plurality of banks
    7.
    发明授权
    Semiconductor memory device having data input/output line shared by a plurality of banks 有权
    具有由多个银行共享的数据输入/输出线的半导体存储器件

    公开(公告)号：US06236616B1

    公开(公告)日：2001-05-22

    申请号：US09513713

    申请日：2000-02-25

    申请人： Su-a Kim ,  Hi-choon Lee

    发明人： Su-a Kim ,  Hi-choon Lee

    IPC分类号： G11C800

    CPC分类号： G11C7/1006

    摘要： A semiconductor memory device having a structure in which a data input/output line is shared by a plurality of banks is provided. In the semiconductor memory device which has a memory block including a plurality of banks, data of a selected memory cell is input or output via a data input/output line. When data is written to a memory cell, the memory block is divided into at least two bank groups and the data input/output line is divided into at least two data input/output lines to separately connect the data input/output line to the respective bank groups so that the data is written to the selected memory cell via the data input/output line connected to a bank group including the selected memory cell. When data of a selected memory cell is read, the local data input/output lines are connected. Therefore, reduction of speed and power consumption is minimized and loads of data input/output lines are regulated during the read and write operations.

    摘要翻译： 提供具有数据输入/输出线由多个存储体共享的结构的半导体存储器件。 在具有包括多个存储体的存储块的半导体存储器件中，经由数据输入/输出线输入或输出所选存储单元的数据。 当数据被写入存储单元时，存储器块被划分为至少两个组组，数据输入/输出线被分成至少两个数据输入/输出线，以将数据输入/输出线分别连接到相应的 以使得经由连接到包括所选存储单元的存储体组的数据输入/输出线将数据写入所选存储单元。 当读取所选存储单元的数据时，连接本地数据输入/输出线。 因此，在读取和写入操作期间，速度和功耗的降低被最小化并且数据输入/输出线的负载被调节。