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    Nonvolatile semiconductor memory capable of simultaneously equalizing bit lines and sense lines
    1.
    发明授权
    Nonvolatile semiconductor memory capable of simultaneously equalizing bit lines and sense lines 失效
    非易失性半导体存储器能够同时均衡位线和感测线

    公开(公告)号：US5559737A

    公开(公告)日：1996-09-24

    申请号：US338827

    申请日：1994-11-10

    申请人： Sumio Tanaka ,  Shigeru Atsumi ,  Masao Kuriyama

    发明人： Sumio Tanaka ,  Shigeru Atsumi ,  Masao Kuriyama

    IPC分类号： G11C17/00 ,  G11C7/12 ,  G11C16/06 ,  G11C16/28

    CPC分类号： G11C7/12 ,  G11C16/28

    摘要： In a nonvolatile semiconductor memory having a two-stage sense read circuit using a level shift circuit and a single-end sense amplifier, relationships of sizes of a main memory cell bit line charge transistor, a main memory cell bit line transfer gate transistor, a main memory cell bit line load transistor, a dummy cell bit line charge transistor, a dummy cell bit line transfer gate transistor, and a dummy cell bit line load transistor are set to simultaneously satisfy conditions for equalizing a bit line and a dummy cell bit line and conditions for equalizing a sense line and a dummy cell sense line. Therefore, the potentials of the bit line and the dummy cell bit line and the potentials of the sense line and the dummy cell sense line can be simultaneously equalized, and a high-speed read operation can be achieved.

    摘要翻译： 在具有使用电平移位电路和单端读出放大器的两级读出电路的非易失性半导体存储器中，主存储单元位线电荷晶体管，主存储单元位线传输栅极晶体管， 主存储单元位线负载晶体管，虚设单元位线充电晶体管，虚设单元位线传输门晶体管和虚设单元位线负载晶体管被设置为同时满足用于对位线和虚设单元位线进行均衡的条件 以及用于均衡感测线和虚拟细胞感测线的条件。 因此，可以同时均衡位线和虚设单元位线的电位和感测线和虚设单元感测线的电位，并且可以实现高速读取操作。

    Nonvolatile semiconductor memory device having row decoder
    2.
    发明授权
    Nonvolatile semiconductor memory device having row decoder 失效
    具有行解码器的非易失性半导体存储器件

    公开(公告)号：US6166987A

    公开(公告)日：2000-12-26

    申请号：US443100

    申请日：1999-11-18

    申请人： Shigeru Atsumi ,  Sumio Tanaka

    发明人： Shigeru Atsumi ,  Sumio Tanaka

    IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C8/00 ,  G11C8/08 ,  G11C16/06 ,  G11C16/08 ,  G11C16/14 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115

    CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/14

    摘要： A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during another modes.

    摘要翻译： 提供了一种非易失性半导体存储器件，其中在擦除模式期间将负电压施加到存储单元晶体管的栅电极。 存储器件包括具有连接到字线的N沟道晶体管的行解码器电路。 N沟道晶体管设置在半导体衬底的P型阱区上。 在擦除模式期间，向P型阱区施加负电压，而在其它模式期间施加接地电位。

    Nonvolatile semiconductor memory device including potential generating circuit
    3.
    发明授权
    Nonvolatile semiconductor memory device including potential generating circuit 失效
    包括电位发生电路的非易失性半导体存储器件

    公开(公告)号：US5875129A

    公开(公告)日：1999-02-23

    申请号：US744821

    申请日：1996-11-06

    申请人： Shigeru Atsumi ,  Sumio Tanaka

    发明人： Shigeru Atsumi ,  Sumio Tanaka

    IPC分类号： H01L21/8247 ,  G11C16/08 ,  G11C16/30 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

    CPC分类号： G11C16/30 ,  G11C16/08 ,  H01L27/105

    摘要： In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

    摘要翻译： 在闪速存储器EEPROM中，在P型半导体衬底中形成存储单元MC。 外围晶体管TR形成在N型阱中。 另一个外围晶体管TR形成在P型阱中。 P型阱依次形成N型阱并与衬底电绝缘。 基板通常设置有金属背部结构，并且其基板电压分别设置为预定电压用于数据擦除，数据存储和数据检索。 通过这样的布置，可以显着地减少在数据擦除期间装载装置的电压应力的水平，以允许对装置实现缩小尺寸和增强的质量。

    Non-volatile semiconductor memory having improved testing circuitry
    4.
    发明授权
    Non-volatile semiconductor memory having improved testing circuitry 失效
    具有改进测试电路的非易失性半导体存储器

    公开(公告)号：US4956816A

    公开(公告)日：1990-09-11

    申请号：US358482

    申请日：1989-05-30

    申请人： Shigeru Atsumi ,  Sumio Tanaka ,  Shinji Saito ,  Nobuaki Otsuka

    发明人： Shigeru Atsumi ,  Sumio Tanaka ,  Shinji Saito ,  Nobuaki Otsuka

    IPC分类号： G11C17/00 ,  G11C16/34 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50

    CPC分类号： G11C29/50004 ,  G11C16/34 ,  G11C29/50 ,  G11C29/50016 ,  G06F2201/81 ,  G11C16/04

    摘要： This invention provides a non-volatile semiconductor memory having a first node and a second node, the second node having a ground potential. The invention includes a plurality of non-volatile memory cells each having a drain and a threshold potential, the cells, for storing data written into the cells at a predetermined normal writing voltage. A plurality of bit lines, each memory cell being connected to one of the bit lines, transfer data to and from the memory cells. A circuit connected to the bit lines simultaneously tests the memory cells of all the bit lines at the normal writing voltage to detect changes in the threshold potential.

    摘要翻译： 本发明提供一种具有第一节点和第二节点的非易失性半导体存储器，第二节点具有接地电位。 本发明包括多个具有漏极和阈值电位的非易失性存储单元，用于存储以预定的正常写入电压写入单元的数据。 多个位线，每个存储单元连接到一个位线，将数据传送到存储单元和从存储单元传送数据。 连接到位线的电路同时以正常写入电压测试所有位线的存储单元，以检测阈值电位的变化。

    High voltage switching circuit in a nonvolatile memory
    5.
    发明授权
    High voltage switching circuit in a nonvolatile memory 失效
    非易失性存储器中的高压开关电路

    公开(公告)号：US4893275A

    公开(公告)日：1990-01-09

    申请号：US173563

    申请日：1988-03-25

    申请人： Sumio Tanaka ,  Shigeru Atsumi ,  Nobuaki Ohtsuka ,  Keniti Imamiya

    发明人： Sumio Tanaka ,  Shigeru Atsumi ,  Nobuaki Ohtsuka ,  Keniti Imamiya

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792 ,  H03K17/693

    CPC分类号： G11C16/12

    摘要： A nonvolatile semiconductor memory device includes a power voltage select circuit that is comprised of first and second power source nodes, an output node, first and second depletion type MOS transistors connected in series between the first power source node and the output node, a third MOS transistor connected between an interconnection point between the first and second depletion type MOS transistors and the second power source node, and a fourth MOS transistor connected between the second power source node and the output node.

    摘要翻译： 非易失性半导体存储器件包括由第一和第二电源节点组成的电源电压选择电路，串联连接在第一电源节点和输出节点之间的输出节点，第一和第二耗尽型MOS晶体管，第三MOS 连接在第一和第二耗尽型MOS晶体管与第二电源节点之间的互连点之间的晶体管，以及连接在第二电源节点和输出节点之间的第四MOS晶体管。

    Nonvolatile semiconductor memory device with a lightly-doped drain structure
    6.
    发明授权
    Nonvolatile semiconductor memory device with a lightly-doped drain structure 失效
    具有轻掺杂漏极结构的非易失性半导体存储器件

    公开(公告)号：US4788663A

    公开(公告)日：1988-11-29

    申请号：US42877

    申请日：1987-04-24

    申请人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

    发明人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

    IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C7/00 ,  H01L29/78

    CPC分类号： G11C16/0441

    摘要： Each memory cell in an EPROM includes two memory cell transistors which share a common floating gate and have two separated drains, one of which is connected to a read bit line and the other of which is connected to write bit line. In this EPROM, the read memory cell transistor of the read bit line has a lower hot electron injection rate than the hot electron injection rate of the write memory cell transistor of the write bit line. A bit line voltage booster is connected to the read bit line.

    摘要翻译： EPROM中的每个存储单元包括两个存储单元晶体管，共享一个公共浮动栅极并具有两个分离的漏极，其中一个连接到读取位线，另一个连接到写入位线。 在该EPROM中，读取位线的读取存储单元晶体管的热电子注入速率低于写入位线的写入存储单元晶体管的热电子注入速率。 位线电压升压器连接到读位线。

    Circuit for changing the voltage level of binary signals
    7.
    发明授权
    Circuit for changing the voltage level of binary signals 失效
    用于改变二进制信号电压电平的电路

    公开(公告)号：US4574273A

    公开(公告)日：1986-03-04

    申请号：US548783

    申请日：1983-11-04

    申请人： Shigeru Atsumi ,  Sumio Tanaka

    发明人： Shigeru Atsumi ,  Sumio Tanaka

    IPC分类号： H01L27/10 ,  G11C16/06 ,  G11C17/00 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H03K19/0185 ,  H03K19/0948 ,  H03K17/10 ,  H03K19/094

    CPC分类号： H03K19/0948 ,  H03K19/018521

    摘要： A voltage converter circuit has an input terminal for receiving an input binary signal and a gate for generating an output binary signal corresponding to the input binary signal. An output signal from the gate is supplied to a first input terminal of an inverter through a transistor and further to a second input terminal of the inverter directly, so as to immediately stabilize the output signal from the voltage converter circuit. The inverter inverts the input signal to a higher-voltage binary signal. When a voltage level of the higher-voltage binary signal reaches a given voltage level while the voltage level of the higher-voltage binary signal changes, a feedback circuit is operated to set the input signal supplied to the first input terminal of the inverter at a higher voltage.

    摘要翻译： 电压转换器电路具有用于接收输入二进制信号的输入端子和用于产生对应于输入二进制信号的输出二进制信号的门。 来自栅极的输出信号通过晶体管被提供给逆变器的第一输入端子，并进一步提供给逆变器的第二输入端子，以便立即稳定来自电压转换器电路的输出信号。 逆变器将输入信号反相到较高电压的二进制信号。 当较高电压二进制信号的电压电平在高电压二进制信号的电压电平变化时达到给定电压电平时，反馈电路被操作以将提供给逆变器的第一输入端的输入信号设置为 电压较高。

    Nonvolatile semiconductor memory device including a circuit for providing a boosted potential
    8.
    发明授权
    Nonvolatile semiconductor memory device including a circuit for providing a boosted potential 失效

    公开(公告)号：US06529414B2

    公开(公告)日：2003-03-04

    申请号：US09978252

    申请日：2001-10-17

    申请人： Shigeru Atsumi ,  Sumio Tanaka

    发明人： Shigeru Atsumi ,  Sumio Tanaka

    IPC分类号： G11C1604

    CPC分类号： G11C16/30 ,  G11C16/08 ,  H01L27/105

    摘要： In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

    Nonvolatile semiconductor memory device
    9.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US06324100B1

    公开(公告)日：2001-11-27

    申请号：US09708471

    申请日：2000-11-09

    申请人： Shigeru Atsumi ,  Sumio Tanaka

    发明人： Shigeru Atsumi ,  Sumio Tanaka

    IPC分类号： G11C1606

    CPC分类号： G11C16/30 ,  G11C16/08 ,  H01L27/105

    摘要： In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

    摘要翻译： 在闪速存储器EEPROM中，在P型半导体衬底中形成存储单元MC。 外围晶体管TR形成在N型阱中。 另一个外围晶体管TR形成在P型阱中。 P型阱依次形成N型阱并与衬底电绝缘。 基板通常设置有金属背部结构，并且其基板电压分别设置为预定电压用于数据擦除，数据存储和数据检索。 通过这样的布置，可以显着地减少在数据擦除期间装载装置的电压应力的水平，以允许对装置实现缩小尺寸和增强的质量。