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    Nonvolatile semiconductor memory capable of simultaneously equalizing bit lines and sense lines
    1.
    发明授权
    Nonvolatile semiconductor memory capable of simultaneously equalizing bit lines and sense lines 失效
    非易失性半导体存储器能够同时均衡位线和感测线

    公开(公告)号：US5559737A

    公开(公告)日：1996-09-24

    申请号：US338827

    申请日：1994-11-10

    申请人： Sumio Tanaka ,  Shigeru Atsumi ,  Masao Kuriyama

    发明人： Sumio Tanaka ,  Shigeru Atsumi ,  Masao Kuriyama

    IPC分类号： G11C17/00 ,  G11C7/12 ,  G11C16/06 ,  G11C16/28

    CPC分类号： G11C7/12 ,  G11C16/28

    摘要： In a nonvolatile semiconductor memory having a two-stage sense read circuit using a level shift circuit and a single-end sense amplifier, relationships of sizes of a main memory cell bit line charge transistor, a main memory cell bit line transfer gate transistor, a main memory cell bit line load transistor, a dummy cell bit line charge transistor, a dummy cell bit line transfer gate transistor, and a dummy cell bit line load transistor are set to simultaneously satisfy conditions for equalizing a bit line and a dummy cell bit line and conditions for equalizing a sense line and a dummy cell sense line. Therefore, the potentials of the bit line and the dummy cell bit line and the potentials of the sense line and the dummy cell sense line can be simultaneously equalized, and a high-speed read operation can be achieved.

    摘要翻译： 在具有使用电平移位电路和单端读出放大器的两级读出电路的非易失性半导体存储器中，主存储单元位线电荷晶体管，主存储单元位线传输栅极晶体管， 主存储单元位线负载晶体管，虚设单元位线充电晶体管，虚设单元位线传输门晶体管和虚设单元位线负载晶体管被设置为同时满足用于对位线和虚设单元位线进行均衡的条件 以及用于均衡感测线和虚拟细胞感测线的条件。 因此，可以同时均衡位线和虚设单元位线的电位和感测线和虚设单元感测线的电位，并且可以实现高速读取操作。

    Non-volatile semiconductor memory device and data erasing method therefor
    4.
    发明授权
    Non-volatile semiconductor memory device and data erasing method therefor 失效
    非挥发性半导体存储器件及其数据擦除方法

    公开(公告)号：US5568419A

    公开(公告)日：1996-10-22

    申请号：US507968

    申请日：1995-07-27

    申请人： Shigeru Atsumi ,  Masao Kuriyama ,  Hironori Banba ,  Akira Umezawa ,  Nobuaki Otsuka

    发明人： Shigeru Atsumi ,  Masao Kuriyama ,  Hironori Banba ,  Akira Umezawa ,  Nobuaki Otsuka

    IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445

    摘要： A memory cell array has a plurality of memory cells formed of EEPROM cells arranged in a matrix form. Data in the memory cells is flash-erased, and after this, word lines other than a selected word line are set to a negative potential and erasing verification for detecting an insufficiently erased memory cell is effected. The flash-erasing and erasing verification are repeatedly effected until no insufficiently erased memory cell is detected. When no insufficiently erased memory cell is detected, word lines other than a selected word line are set to a negative potential and an overerased memory cell is detected. When an overerased memory cell is detected, weak program is effected for the cell by applying a voltage lower than the normal writing voltage to the cell.

    摘要翻译： 存储单元阵列具有以矩阵形式布置的EEPROM单元形成的多个存储单元。 存储器单元中的数据被闪存擦除，之后，除了所选字线之外的字线被设置为负电位，并且实现用于检测不充分擦除的存储器单元的擦除验证。 重复进行闪光擦除和擦除验证，直到没有检测到不充分擦除的存储单元。 当没有检测到不充分擦除的存储单元时，除了所选字线以外的字线被设置为负电位，并且检测到过高的存储单元。 当检测到过高的存储单元时，通过将低于正常写入电压的电压施加到单元来对单元进行弱程序。

    Semiconductor integrated circuit device with erasable and programmable fuse memory
    5.
    发明授权
    Semiconductor integrated circuit device with erasable and programmable fuse memory 失效
    具有可擦除和可编程保险丝存储器的半导体集成电路器件

    公开(公告)号：US06856543B2

    公开(公告)日：2005-02-15

    申请号：US10743385

    申请日：2003-12-23

    申请人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    发明人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    IPC分类号： G11C5/00 ,  G11C5/14 ,  G11C16/04 ,  H01L29/78 ,  H03K5/153 ,  H03K5/22

    CPC分类号： G11C5/143 ,  G11C5/14 ,  G11C7/1045 ,  G11C16/26 ,  G11C16/30

    摘要： A semiconductor integrated circuit device includes fuse cells arranged at a fuse cell array, a fuse cell data program and erase circuit, a fuse cell data control circuit, and fuse data latch circuits. The fuse cells include erasable and programmable nonvolatile memory cells. The fuse cell data program and erase circuit programs fuse data to the memory cells and erases the fuse data from the memory cells. The fuse cell data control circuit controls read out timing of the fuse data stored in the memory cells based on a signal generated upon detection of power-on. The fuse data latch circuits latch the fuse data read out from the memory cells.

    摘要翻译： 半导体集成电路器件包括设置在熔丝单元阵列处的熔丝单元，熔丝单元数据程序和擦除电路，熔丝单元数据控制电路和熔丝数据锁存电路。 熔丝单元包括可擦除和可编程的非易失性存储单元。 熔丝单元数据程序和擦除电路程序将数据熔化到存储单元，并从存储单元擦除熔丝数据。 熔丝单元数据控制电路基于在检测到通电时产生的信号来控制存储在存储单元中的熔丝数据的读出定时。 熔丝数据锁存电路锁存从存储器单元读出的熔丝数据。

    Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing
    6.
    发明授权
    Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing 失效
    非易失性半导体存储器，其中编程或擦除位的数量随着编程或擦除的进行而增加

    公开(公告)号：US06222773B1

    公开(公告)日：2001-04-24

    申请号：US09592661

    申请日：2000-06-13

    申请人： Tooru Tanzawa ,  Nobuaki Otsuka ,  Hironori Banba ,  Shigeru Atsumi ,  Masao Kuriyama ,  Seiichi Mori ,  Seiji Yamada

    发明人： Tooru Tanzawa ,  Nobuaki Otsuka ,  Hironori Banba ,  Shigeru Atsumi ,  Masao Kuriyama ,  Seiichi Mori ,  Seiji Yamada

    IPC分类号： G11C1600

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/14

    摘要： A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines. The programming load increases the number of programming bits with the progress of programming when data of plural bits is programmed into a plurality of memory cells simultaneously selected by the cell selection circuit.

    摘要翻译： NOR型闪速存储器包括多个字线，多个位线，至少一个位线，多个非易失性存储器单元，行解码器，单元选择电路和编程负载。 多个非易失性存储单元中的每一个包括栅电极，漏电极和源电极，并且栅电极连接到多个字线中的相应一个字线，漏极连接到多个位线中的相应一个位线 并且源极连接到源极线。 行解码器在数据编程时选择多个字线之一。 单元选择电路包括列解码器和列门，并被构造为从多个位线中的多个组中的每一个同时选择一个位线。 当多个位的数据被编程到由单元选择电路同时选择的多个存储单元中时，编程负载增加了编程进程的编程位数。

    Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing
    7.
    发明授权
    Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing 有权
    非易失性半导体存储器，其中编程或擦除位的数量随着编程或擦除的进行而增加

    公开(公告)号：US06118697A

    公开(公告)日：2000-09-12

    申请号：US324775

    申请日：1999-06-03

    申请人： Tooru Tanzawa ,  Nobuaki Otsuka ,  Hironori Banba ,  Shigeru Atsumi ,  Masao Kuriyama ,  Seiichi Mori ,  Seiji Yamada

    发明人： Tooru Tanzawa ,  Nobuaki Otsuka ,  Hironori Banba ,  Shigeru Atsumi ,  Masao Kuriyama ,  Seiichi Mori ,  Seiji Yamada

    IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/00

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/14

    摘要： A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines. The programming load increases the number of programming bits with the progress of programming when data of plural bits is programmed into a plurality of memory cells simultaneously selected by the cell selection circuit.

    摘要翻译： NOR型闪速存储器包括多个字线，多个位线，至少一个位线，多个非易失性存储器单元，行解码器，单元选择电路和编程负载。 多个非易失性存储单元中的每一个包括栅电极，漏电极和源电极，并且栅电极连接到多个字线中的相应一个字线，漏极连接到多个位线中的相应一个位线 并且源极连接到源极线。 行解码器在数据编程时选择多个字线之一。 单元选择电路包括列解码器和列门，并被构造为从多个位线中的多个组中的每一个同时选择一个位线。 当多个位的数据被编程到由单元选择电路同时选择的多个存储单元中时，编程负载增加了编程进程的编程位数。

    Semiconductor memory device having improved cell array layout
    8.
    发明授权
    Semiconductor memory device having improved cell array layout 失效
    具有改善的单元阵列布局的半导体存储器件

    公开(公告)号：US6064618A

    公开(公告)日：2000-05-16

    申请号：US30997

    申请日：1998-02-26

    申请人： Masao Kuriyama ,  Shigeru Atsumi

    发明人： Masao Kuriyama ,  Shigeru Atsumi

    IPC分类号： G11C16/04 ,  G11C5/02 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  G11C8/00

    CPC分类号： G11C5/025

    摘要： Each of first and second cell array groups has a cell array and a row decoder. Circuit blocks including a reset transistor, a Y selector, a write transistor, a block decoder, and a source decoder except the cell array and row decoder are arranged in the area between the first and second cell array groups. Since an address signal, a control signal, and a power supply common to the circuit blocks can be shared, the layout area can be reduced.

    摘要翻译： 第一和第二单元阵列组中的每一个具有单元阵列和行解码器。 包括复位晶体管，Y选择器，写入晶体管，块解码器和除了单元阵列和行解码器之外的源解码器的电路块布置在第一和第二单元阵列组之间的区域中。 由于可以共享地址信号，控制信号和电路块共用的电源，因此可以减小布局面积。

    Semiconductor memory device having improved cell array layout
    10.
    发明授权
    Semiconductor memory device having improved cell array layout 失效
    具有改善的单元阵列布局的半导体存储器件

    公开(公告)号：US06205045B1

    公开(公告)日：2001-03-20

    申请号：US09544293

    申请日：2000-04-06

    申请人： Masao Kuriyama ,  Shigeru Atsumi

    发明人： Masao Kuriyama ,  Shigeru Atsumi

    IPC分类号： G11C506

    CPC分类号： G11C5/025

    摘要： Each of first and second cell array groups has a cell array and a row decoder. Circuit blocks including a reset transistor, a Y selector, a write transistor, a block decoder, and a source decoder except the cell array and row decoder are arranged in the area between the first and second cell array groups. Since an address signal, a control signal, and a power supply common to the circuit blocks can be shared, the layout area can be reduced.

    摘要翻译： 第一和第二单元阵列组中的每一个具有单元阵列和行解码器。 包括复位晶体管，Y选择器，写入晶体管，块解码器和除了单元阵列和行解码器之外的源解码器的电路块布置在第一和第二单元阵列组之间的区域中。 由于可以共享地址信号，控制信号和电路块公用的电源，所以可以减小布局面积。