摘要:
A semiconductor device having trap sites passivated with deuterium has enhanced immunity to hot carrier effects. The trap sites which are passivated with deuterium are encapsulated beneath a barrier film and are therefore resistant to having the deuterium diffuse away from the trap sites during subsequent high temperature processing operations.
摘要:
A process sequence for forming a semiconductor device utilizes a passivation annealing process using deuterium which enhances immunity to hot carrier effects and extends device lifetime. The process sequence is carried out prior to the introduction of metal conductive films to the device. The process sequence includes a three-step passivation, de-passivation, re-passivation sequence and utilizes a barrier film to encapsulate deuterium molecules in the vicinity of a gate oxide, during the de-passivation operation.
摘要:
The present invention provides a method of determining a trap density of a semiconductor substrate/dielectric interface. In one embodiment, the method comprises measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, wherein the measured current is a function of the number of traps located at the interface, and determining the trap density as a function of the measured current.
摘要:
An automated system for, and method of estimating ring oscillator reliability and testing AC response of a device under test (DUT). In one embodiment, the system includes: (1) a DUT board that accepts, and allows electrical communication with, a plurality of DUTs, (2) a power source, couplable to the DUT board, that provides AC power of controllable characteristics to the plurality of DUTs and (3) an automated switching matrix, couplable between the DUT board and a circuit analyzer, that allows the circuit analyzer to analyze ring oscillators and predetermined portions of the plurality of DUTs at predetermined times as the power source provides the power thereto.
摘要:
The present invention provides a method of forming a metal oxide metal (MOM) capacitor on a substrate, such as a silicon substrate, of a semiconductor wafer in a rapid thermal process (RTP) machine. The MOM capacitor is fabricated by forming a metal layer on the semiconductor substrate. The metal layer is then subjected to a first rapid thermal process in a substantially inert but nitrogen-free atmosphere that consumes a portion of the metal layer to form a first metal electrode layer and a silicide layer between the first metal electrode and the semiconductor substrate. The semiconductor wafer is then subjected to a second rapid thermal process. During this process, the remaining portion of the metal layer is oxidized to form a metal oxide on the first metal electrode, which serves as the dielectric layer of the MOM capacitor. Following the formation of the dielectric layer, a second metal electrode layer is then conventionally formed on the metal oxide, which completes the formation of the MOM capacitor. Preferably, the first electrode layer and the metal oxide layer are formed in a single RTP machine.
摘要:
The present invention provides a method of forming a metal oxide metal (MOM)capacitor on a substrate, such as a silicon substrate, of a semiconductor wafer in a rapid thermal process (RTP) machine. The MOM capacitor is fabricated by forming a metal layer on the semiconductor substrate. The metal layer is then subjected to a first rapid thermal process in a substantially inert but nitrogen-free atmosphere that consumes a portion of the metal layer to form a first metal electrode layer and a silicide layer between the first metal electrode and the semiconductor substrate. The semiconductor wafer is then subjected to a second rapid thermal process. During this process, the remaining portion of the metal layer is oxidized to form a metal oxide on the first metal electrode, which serves as the dielectric layer of the MOM capacitor. Following the formation of the dielectric layer, a second metal electrode layer is then conventionally formed on the metal oxide, which completes the formation of the MOM capacitor. Preferably, the first electrode layer and the metal oxide layer are formed in a single RTP machine.
摘要:
Methods for producing in-situ grooves in CMP pads are provided. In general, the methods for producing in-situ grooves comprise the steps of patterning a silicone lining, placing the silicone lining in, or on, a mold, adding CMP pad material to the silicone lining, and allowing the CMP pad to solidify. CMP pads comprising novel groove designs are also described. For example, described here are CMP pads comprising concentric circular grooves and axially curved grooves, reverse logarithmic grooves, overlapping circular grooves, lassajous groves, double spiral grooves, and multiply overlapping axially curved grooves. The CMP pads may be made from polyurethane, and the grooves produced therein may be made by a method from the group consisting of silicone lining, laser writing, water jet cutting, 3-D printing, thermoforming, vacuum forming, micro-contact printing, hot stamping, and mixtures thereof.
摘要:
A multi-piece food product (10) comprising a plurality of strands (12A-12K) that are extruded and aggregated to form an aesthetically pleasing food product is provided. A formulation used to make each of the strands (12A-12K) includes a mixture comprising at least 20% sweetener, at least 15% starchy material, and at least 1% fruit by weight based a total dry weight of the mixture to yield a starch-based confectionary food product. One process for forming the multi-piece food product (10) includes extruding a food stream from a slurry, dividing the food stream into three separate food streams (24A, 24B), injecting color, flavor, and ascorbic acid into the food streams (24A, 24B), conveying the food streams (24A, 24B) into a former (26) and extruding the strands (12A-12K) therefrom, forming the strands (12A, 12B) into an aggregate food mass (31), cooling the food mass (31), and cutting the food mass (31) into individual portions.
摘要:
The present application relates to polishing pads for chemical mechanical planarization (CMP) of substrates, and methods of fabrication and use thereof. The pads described in this invention are customized to polishing specifications where specifications include (but not limited to) to the material being polished, chip design and architecture, chip density and pattern density, equipment platform and type of slurry used. These pads can be designed with a specialized polymeric nano-structure with a long or short range order which allows for molecular level tuning achieving superior thermo-mechanical characteristics. More particularly, the pads can be designed and fabricated so that there is both uniform and nonuniform spatial distribution of chemical and physical properties within the pads. In addition, these pads can be designed to tune the coefficient of friction by surface engineering, through the addition of solid lubricants, and creating low shear integral pads having multiple layers of polymeric material which form an interface parallel to the polishing surface. The pads can also have controlled porosity, embedded abrasive, novel grooves on the polishing surface, for slurry transport, which are produced in situ, and a transparent region for endpoint detection.
摘要:
The present invention provides a composite polishing pad, comprising. In an advantageous embodiment, the composite polishing pad includes a polishing pad member comprising a material having a predetermined hardness and an annular support member underlying a periphery of the polishing pad member, the annular support member having a hardness less than the predetermined hardness of the polishing pad member.