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    CMOS static random access memory devices
    1.
    发明授权
    CMOS static random access memory devices 有权
    CMOS静态随机存取存储器件

    公开(公告)号：US6147385A

    公开(公告)日：2000-11-14

    申请号：US218819

    申请日：1998-12-22

    申请人： Sung-Bong Kim ,  Ki-Joon Kim ,  Jong-Mil Youn

    发明人： Sung-Bong Kim ,  Ki-Joon Kim ,  Jong-Mil Youn

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

    摘要： A full CMOS SRAM cell having the capability of having a reduced aspect ratio is described. The SRAM cell includes first and second transfer transistors of n-channel types, first and second driving transistors of the n-channel types and first and second load transistors of p-channel types. Each of the transistors has source and drain regions on opposite sides of a channel region formed in a semiconductor substrate and a gate over the channel region. The cell includes a first common region defined by the drain regions of the first transfer transistor and the first driving transistor connected in series therethrough. A second common region is defined by the drain regions of the second transfer transistor and the second driving transistor connected in series therethrough. The drain region of the first load transistor is disposed adjacent to the first common region between the first and second common regions. The drain region of the second load transistor is disposed between the drain region of the first load transistor and the second common region. First and second gate electrode layers are disposed generally parallel to each other, and respectively serving as the gates of the first driving transistor and the first load transistor and as the gates of the second driving transistor and the second load transistor, wherein each of the first and second gate electrode layers is made of a conductive material of a first level. First and second interconnecting layers are each made of a conductive material of a second level different from the first level, the first interconnecting layer connecting the first common region to the drain region of the first load transistor and the second gate electrode layer, the second interconnecting layer connecting the second common region to the drain region of the second load transistor and the first gate electrode layer.

    摘要翻译： 描述具有减小的纵横比的能力的完整CMOS SRAM单元。 SRAM单元包括n沟道类型的第一和第二传输晶体管，n沟道类型的第一和第二驱动晶体管以及p沟道类型的第一和第二负载晶体管。 每个晶体管在形成在半导体衬底中的沟道区的相对侧上具有源极和漏极区域，并且在沟道区域上具有栅极。 单元包括由第一传输晶体管的漏极区域和串联连接的第一驱动晶体管限定的第一公共区域。 第二公共区域由第二传输晶体管和串联连接的第二驱动晶体管的漏极区限定。 第一负载晶体管的漏极区域设置成与第一和第二公共区域之间的第一公共区域相邻。 第二负载晶体管的漏极区域设置在第一负载晶体管的漏极区域和第二公共区域之间。 第一和第二栅极电极层大体上彼此平行地设置，并且分别用作第一驱动晶体管和第一负载晶体管的栅极，以及作为第二驱动晶体管和第二负载晶体管的栅极，其中第一 并且第二栅电极层由第一级的导电材料制成。 第一和第二互连层各自由不同于第一电平的第二电平的导电材料制成，第一互连层将第一公共区域连接到第一负载晶体管的漏极区域和第二栅极电极层，第二互连 将第二公共区域连接到第二负载晶体管的漏极区域和第一栅极电极层的层。

    Method for manufacturing semiconductor device
    2.
    发明授权
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US6165900A

    公开(公告)日：2000-12-26

    申请号：US233482

    申请日：1999-01-20

    申请人： Ki-Joon Kim ,  Jong-mil Youn ,  Sung-Bong Kim

    发明人： Ki-Joon Kim ,  Jong-mil Youn ,  Sung-Bong Kim

    IPC分类号： H01L21/24 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8244 ,  H01L21/4763

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76895 ,  H01L27/11

    摘要： A semiconductor device manufacturing method is provided. In this method for interconnecting conductive layers, an insulating layer is formed over the surface of a semiconductor substrate having conductive layers formed thereon. The insulating layer is removed from over the conductive layers and a silicon layer is coated on the overall surface of the resultant structure. The insulating layer and some silicon are then removed from an area except for the area from a first conductive layer through a second conductive layer, and a refractory metal layer is formed on the overall surface of the resultant structure. This refractory metal is used for silicidation. A metal silicide layer is then formed from the first conductive layer through the second conductive layer by thermally treating the refractory metal layer.

    摘要翻译： 提供了一种半导体器件制造方法。 在用于互连导电层的方法中，在其上形成有导电层的半导体衬底的表面上形成绝缘层。 从导电层上除去绝缘层，并在所得结构的整个表面上涂覆硅层。 然后从除了通过第二导电层的第一导电层的区域之外的区域除去绝缘层和一些硅，并且在所得结构的整个表面上形成难熔金属层。 该难熔金属用于硅化。 然后通过对难熔金属层进行热处理，由第一导电层通过第二导电层形成金属硅化物层。

    CONSTANT-VELOCITY JOINT ASSEMBLY
    4.
    发明申请
    CONSTANT-VELOCITY JOINT ASSEMBLY 有权
    恒速联合总成

    公开(公告)号：US20140113734A1

    公开(公告)日：2014-04-24

    申请号：US14119601

    申请日：2012-04-09

    申请人： In-Woo Lee ,  Ho-Chul Son ,  Hyun-Chul Kim ,  Sung-Bong Kim ,  Moo-Young Park ,  Se-Hun Jung

    发明人： In-Woo Lee ,  Ho-Chul Son ,  Hyun-Chul Kim ,  Sung-Bong Kim ,  Moo-Young Park ,  Se-Hun Jung

    IPC分类号： F16D3/32

    CPC分类号： F16D3/26 ,  F16D3/30 ,  F16D3/32 ,  F16D3/33

    摘要： A constant-velocity joint assembly includes: a first and a second shaft portions respectively provided with a protrusion; a double yoke portion in which a guide hole is formed along an axis direction, the first and the second shaft portions being respectively rotatably connected to both sides of the guide hole with an axis of an upper/lower direction; and a guide portion which is disposed to the guide hole to guide the protrusion and rotates along an inner circumference of the guide hole during rotation of the shaft portions, wherein the first and the second shaft portions respectively comprises: a spider body, a left and a right leg, and an upper and a lower legs; a shaft provided with the protrusion; and a yoke block comprising a block body, and a left and a right connecting member.

    摘要翻译： 恒速接头组件包括：分别设置有突起的第一和第二轴部; 沿着轴方向形成有导向孔的双轭部，所述第一轴部和所述第二轴部分分别以所述上下方向的轴线可旋转地连接在所述引导孔的两侧; 以及引导部，其设置在所述引导孔中，以在所述轴部旋转期间引导所述突起并沿着所述引导孔的内周旋转，其中所述第一和第二轴部分别包括：蜘蛛体， 右腿，上腿和下腿; 设置有突起的轴; 以及包括块体的轭块，以及左右连接构件。

    Layouts for CMOS SRAM cells and devices
    5.
    发明授权
    Layouts for CMOS SRAM cells and devices 有权
    CMOS SRAM单元和器件的布局

    公开(公告)号：US06870231B2

    公开(公告)日：2005-03-22

    申请号：US10292180

    申请日：2002-11-12

    申请人： Sung-Bong Kim ,  Soon-Moon Jung ,  Jae-Kyun Park

    发明人： Sung-Bong Kim ,  Soon-Moon Jung ,  Jae-Kyun Park

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H10L31/119

    CPC分类号： H01L27/11 ,  H01L27/1104

    摘要： SRAM cells and devices are provided. The SRAM cells may share connections with neighboring cells, including ground, power supply voltage and/or bit line connections. SRAM cells and devices are also provided that include first and second active regions disposed at a semiconductor substrate. Parallel first and second gate electrodes cross over the first and second active regions. One end of the first active region adjacent to the first gate electrode is electrically connected to the second active region adjacent to the first gate electrode through a first node line parallel to the first gate electrode, and the other end of the first active region adjacent to the second gate electrode is electrically connected to the second active region adjacent to the second gate electrode through a second node line parallel to the second gate electrode. The first node line is electrically connected to the second gate electrode through a first local interconnection crossing over the first node line, and the second node line is electrically connected to the first gate electrode through a second local interconnection crossing over the second node line. Additionally, a word line may be in direct contact with gate electrodes of transfer transistors of the SRAM cells.

    摘要翻译： 提供SRAM单元和器件。 SRAM单元可以与相邻单元共享连接，包括地，电源电压和/或位线连接。 还提供了包括设置在半导体衬底上的第一和第二有源区的SRAM单元和器件。 平行的第一和第二栅电极跨过第一和第二有源区。 与第一栅极相邻的第一有源区的一端通过与第一栅电极平行的第一节点线与第一栅电极相邻的第二有源区电连接，并且与第一有源区相邻的第一有源区的另一端 第二栅电极通过与第二栅电极平行的第二节点线电连接到与第二栅电极相邻的第二有源区。 第一节点线通过跨第一节点线的第一局部互连电连接到第二栅极电极，并且第二节点线通过跨第二节点线的第二局部互连电连接到第一栅电极。 此外，字线可以与SRAM单元的转移晶体管的栅电极直接接触。

    Joint assembly
    6.
    发明授权
    Joint assembly 有权
    联合装配

    公开(公告)号：US09228614B2

    公开(公告)日：2016-01-05

    申请号：US14119601

    申请日：2012-04-09

    申请人： In-Woo Lee ,  Ho-Chul Son ,  Hyun-Chul Kim ,  Sung-Bong Kim ,  Moo-Young Park ,  Se-Hun Jung

    发明人： In-Woo Lee ,  Ho-Chul Son ,  Hyun-Chul Kim ,  Sung-Bong Kim ,  Moo-Young Park ,  Se-Hun Jung

    IPC分类号： F16D3/26 ,  F16D3/30 ,  F16D3/32 ,  F16D3/33

    CPC分类号： F16D3/26 ,  F16D3/30 ,  F16D3/32 ,  F16D3/33

    摘要： A constant-velocity joint assembly includes: a first and a second shaft portions respectively provided with a protrusion; a double yoke portion in which a guide hole is formed along an axis direction, the first and the second shaft portions being respectively rotatably connected to both sides of the guide hole with an axis of an upper/lower direction; and a guide portion which is disposed to the guide hole to guide the protrusion and rotates along an inner circumference of the guide hole during rotation of the shaft portions, wherein the first and the second shaft portions respectively comprises: a spider body, a left and a right leg, and an upper and a lower legs; a shaft provided with the protrusion; and a yoke block comprising a block body, and a left and a right connecting member.

    摘要翻译： 恒速接头组件包括：分别设置有突起的第一和第二轴部; 沿着轴方向形成有导向孔的双轭部，所述第一轴部和所述第二轴部分分别以所述上下方向的轴线可旋转地连接在所述引导孔的两侧; 以及引导部，其设置在所述引导孔中，以在所述轴部旋转期间引导所述突起并沿着所述引导孔的内周旋转，其中所述第一和第二轴部分别包括：蜘蛛体， 右腿，上腿和下腿; 设置有突起的轴; 以及包括块体的轭块，以及左右连接构件。

    Semiconductor device having silicide thin film and method of forming the same
    7.
    发明授权
    Semiconductor device having silicide thin film and method of forming the same 有权
    具有硅化物薄膜的半导体器件及其形成方法

    公开(公告)号：US07385260B2

    公开(公告)日：2008-06-10

    申请号：US10830390

    申请日：2004-04-21

    申请人： Hyung-Shin Kwon ,  Joon-Yong Joo ,  Kwang-Ok Koh ,  Sung-Bong Kim

    发明人： Hyung-Shin Kwon ,  Joon-Yong Joo ,  Kwang-Ok Koh ,  Sung-Bong Kim

    IPC分类号： H01L29/861

    CPC分类号： H01L29/66507 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545

    摘要： The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.

    摘要翻译： 本发明提供一种具有硅化物薄膜的半导体器件及其形成方法。 半导体器件包括形成在半导体衬底的有源区上的栅极绝缘层。 在栅极绝缘层上形成栅电极。 在与栅电极相邻的有源区中形成杂质区。 诸如硅化钴薄膜的硅化物薄膜在杂质区域中形成为小于约200埃的厚度。

    Semiconductor device having a multi-level metallization and its fabricating method
    8.
    发明授权
    Semiconductor device having a multi-level metallization and its fabricating method 有权
    具有多层金属化的半导体器件及其制造方法

    公开(公告)号：US06448651B1

    公开(公告)日：2002-09-10

    申请号：US09396147

    申请日：1999-09-15

    申请人： Sung-Bong Kim

    发明人： Sung-Bong Kim

    IPC分类号： H01L2940

    CPC分类号： H01L21/76897 ,  H01L21/76838 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a semiconductor device having a multi-level metallization. The device includes a semiconductor substrate having an active area, a first insulating layer deposited on the substrate, and first and second contact holes penetrating the first insulating layer exposing a predetermined surface of the active area. First and second conductive plugs are formed in the first and second contact holes, respectively. First and second conductive patterns are spaced a predetermined distance on both sides of the second conductive plug. The first conductive pattern is connected to the first conductive plug. An etching prevention layer and a second insulating layer are sequentially formed on the resultant structure. A third contact hole penetrates the second insulating layer and the etching prevention layer exposes a predetermined surface of the first conductive pattern. A fourth contact hole penetrates the second insulating layer and the etching prevention layer to expose the surface of the second conductive plug. Third and fourth conductive plugs are formed in the third and fourth contact holes, respectively. Third and fourth conductive patterns are individually formed on a predetermined area of the second insulating layer to be connected with the third and fourth conductive plugs, respectively.

    摘要翻译： 提供了具有多层金属化的半导体器件。 该器件包括具有有源区的半导体衬底，沉积在衬底上的第一绝缘层，以及暴露有源区的预定表面的穿透第一绝缘层的第一和第二接触孔。 第一和第二导电插塞分别形成在第一和第二接触孔中。 第一导电图案和第二导电图案在第二导电插塞的两侧隔开预定的距离。 第一导电图案连接到第一导电插头。 在所得结构上依次形成防蚀层和第二绝缘层。 第三接触孔穿透第二绝缘层，并且防蚀层暴露第一导电图案的预定表面。 第四接触孔穿透第二绝缘层和防腐蚀层以露出第二导电插塞的表面。 第三和第四导电插头分别形成在第三和第四接触孔中。 第三和第四导电图案分别形成在第二绝缘层的预定区域上，以分别与第三和第四导电插塞连接。