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    Method of fabricating nonvolatile memory device
    1.
    发明申请
    Method of fabricating nonvolatile memory device 审中-公开
    制造非易失性存储器件的方法

    公开(公告)号：US20080076242A1

    公开(公告)日：2008-03-27

    申请号：US11893063

    申请日：2007-08-14

    申请人： Sung-Gon Choi ,  Hyun-Khe Yoo ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

    发明人： Sung-Gon Choi ,  Hyun-Khe Yoo ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

    IPC分类号： H01L21/3205

    CPC分类号： H01L27/11526 ,  H01L27/11546

    摘要： A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region. Cell gate patterns are formed in the cell array region, and peripheral gate patterns are formed in the peripheral circuit region. Each of the cell gate patterns includes a control gate pattern and a capping pattern, and each of the peripheral gate patterns has a smaller thickness than the cell gate pattern. An interlayer dielectric layer is formed on the resultant structure having the cell gate patterns and the peripheral gate patterns. The interlayer dielectric layer is planarized by etching until the top surface of the capping pattern is exposed, so that an interlayer dielectric pattern is formed. The interlayer dielectric pattern covers the peripheral circuit region and fills a space between the cell gate patterns. An ion implantation process is performed using the interlayer dielectric pattern as an ion mask so that impurity ions are selectively implanted into the control gate pattern.

    摘要翻译： 制造非易失性存储器件的方法包括制备具有单元阵列区域和外围电路区域的半导体衬底。 在单元阵列区域中形成单元栅极图案，并且在外围电路区域中形成外围栅极图案。 每个单元栅极图案包括控制栅极图案和封盖图案，并且每个外围栅极图案具有比单元栅极图案更小的厚度。 在具有单元栅极图案和外围栅极图案的合成结构上形成层间介电层。 通过蚀刻来平坦化层间绝缘层，直到覆盖图案的顶表面露出，形成层间电介质图案。 层间电介质图案覆盖外围电路区域并填充单元栅极图案之间的空间。 使用层间电介质图案作为离子掩模进行离子注入工艺，使得杂质离子被选择性地注入到控制栅极图案中。

    Non-volatile memory device and method of operating the same
    2.
    发明授权
    Non-volatile memory device and method of operating the same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US07697336B2

    公开(公告)日：2010-04-13

    申请号：US11903482

    申请日：2007-09-21

    申请人： Chang-Min Jeon ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Sung-Gon Choi ,  Bo-Young Seo ,  Ji-Do Ryu

    发明人： Chang-Min Jeon ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Sung-Gon Choi ,  Bo-Young Seo ,  Ji-Do Ryu

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0433 ,  H01L27/115 ,  H01L27/11524

    摘要： The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled.

    摘要翻译： 本发明涉及一种非易失性存储器件及其操作方法。 非易失性存储器件包括连接到第n位线的第一晶体管和连接到第（n + 1）位线的第二晶体管。 第一晶体管和第二晶体管串联耦合在第n位线和第（n + 1）位线之间。 非易失性存储器件可以包括2晶体管1位单元，其中存储单元的漏极区域和源极区域具有相同或相似的结构。 由于根据本发明的非易失性存储器件的单元阵列可以包括2-晶体管2位单位单元，所以非易失性存储器件的存储容量可以加倍。

    Non-volatile memory device, method of manufacturing the same and method of operating the same
    3.
    发明授权
    Non-volatile memory device, method of manufacturing the same and method of operating the same 失效
    非易失性存储器件，其制造方法及其操作方法

    公开(公告)号：US07696561B2

    公开(公告)日：2010-04-13

    申请号：US11870762

    申请日：2007-10-11

    申请人： Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

    发明人： Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.

    摘要翻译： 非易失性存储器件包括第一感测线，第一字线，耗尽沟道区和杂质区。 第一感测线和第一字线在基板上彼此平行地相邻地形成。 第一感测线和第一字线具有依次层叠在衬底上的隧道氧化物层，第一导电图案，电介质层图案和第二导电图案。 耗尽沟道区形成在第一感测线下方的衬底的上部。 在由第一感测线和第一字线露出的衬底的上部形成杂质区。

    Non-volatile memory device
    4.
    发明授权
    Non-volatile memory device 有权
    非易失性存储器件

    公开(公告)号：US07512003B2

    公开(公告)日：2009-03-31

    申请号：US11789003

    申请日：2007-04-23

    申请人： Hyun-Khe Yoo ,  Ji-Do Ryu ,  Bo-Young Seo ,  Chang-Min Jeon ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Jeong-Uk Han

    发明人： Hyun-Khe Yoo ,  Ji-Do Ryu ,  Bo-Young Seo ,  Chang-Min Jeon ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Jeong-Uk Han

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0433 ,  G11C7/18 ,  G11C16/24 ,  G11C2207/002

    摘要： A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.

    摘要翻译： 非易失性存储器件包括存储器单元块，第一切换块和第二切换块。 多个存储单元布置在存储单元块中，并且每个存储单元包括具有浮置栅极和控制栅极的存储晶体管，并连接到局部位线，并且包括串联连接到存储晶体管的选择晶体管 它连接到源线。 第一切换块选择性地将全局位线连接到本地位线，而第二切换块以预定位数为单位来控制存储单元块中的存储单元。 第一切换块包括在全局位线和局部位线之间并联连接的至少两个开关器件。

    Non-volatile memory device and method of operating the same
    5.
    发明申请
    Non-volatile memory device and method of operating the same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US20080253190A1

    公开(公告)日：2008-10-16

    申请号：US11903482

    申请日：2007-09-21

    申请人： Chang-Min Jeon ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Sung-Gon Choi ,  Bo-Young Seo ,  Ji-Do Ryu

    发明人： Chang-Min Jeon ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Sung-Gon Choi ,  Bo-Young Seo ,  Ji-Do Ryu

    IPC分类号： G11C16/06 ,  H01L29/788

    CPC分类号： G11C16/0433 ,  H01L27/115 ,  H01L27/11524

    摘要： The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled.

    摘要翻译： 本发明涉及一种非易失性存储器件及其操作方法。 非易失性存储器件包括连接到第n位线的第一晶体管和连接到第（n + 1）位线的第二晶体管。 第一晶体管和第二晶体管串联耦合在第n位线和第（n + 1）位线之间。 非易失性存储器件可以包括2晶体管1位单元，其中存储单元的漏极区域和源极区域具有相同或相似的结构。 由于根据本发明的非易失性存储器件的单元阵列可以包括2-晶体管2位单位单元，所以非易失性存储器件的存储容量可以加倍。

    NON-VOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME AND METHOD OF OPERATING THE SAME
    6.
    发明申请
    NON-VOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME AND METHOD OF OPERATING THE SAME 失效
    非易失性存储器件，其制造方法及其操作方法

    公开(公告)号：US20080089136A1

    公开(公告)日：2008-04-17

    申请号：US11870762

    申请日：2007-10-11

    申请人： Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

    发明人： Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

    IPC分类号： G11C11/34 ,  H01L21/336 ,  H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.

    摘要翻译： 非易失性存储器件包括第一感测线，第一字线，耗尽沟道区和杂质区。 第一感测线和第一字线在基板上彼此平行地相邻地形成。 第一感测线和第一字线具有依次层叠在衬底上的隧道氧化物层，第一导电图案，电介质层图案和第二导电图案。 耗尽沟道区形成在第一感测线下方的衬底的上部。 在由第一感测线和第一字线露出的衬底的上部形成杂质区。

    Non-Volatile memory device
    7.
    发明申请
    Non-Volatile memory device 有权
    非易失性存储器件

    公开(公告)号：US20080008003A1

    公开(公告)日：2008-01-10

    申请号：US11789003

    申请日：2007-04-23

    申请人： Hyun-Khe Yoo ,  Ji-Do Ryu ,  Bo-Young Seo ,  Chang-Min Jeon ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Jeong-Uk Han

    发明人： Hyun-Khe Yoo ,  Ji-Do Ryu ,  Bo-Young Seo ,  Chang-Min Jeon ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Jeong-Uk Han

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0433 ,  G11C7/18 ,  G11C16/24 ,  G11C2207/002

    摘要： A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.

    摘要翻译： 非易失性存储器件包括存储器单元块，第一切换块和第二切换块。 多个存储单元布置在存储单元块中，并且每个存储单元包括具有浮置栅极和控制栅极的存储晶体管，并连接到局部位线，并且包括串联连接到存储晶体管的选择晶体管 它连接到源线。 第一切换块选择性地将全局位线连接到本地位线，并且第二切换块以预定位数为单位来控制存储单元块中的存储单元。 第一切换块包括在全局位线和局部位线之间并联连接的至少两个开关器件。

    NON-VOLATILE MEMORY DEVICE, SYSTEM, AND CELL ARRAY
    8.
    发明申请
    NON-VOLATILE MEMORY DEVICE, SYSTEM, AND CELL ARRAY 有权
    非易失性存储器件，系统和细胞阵列

    公开(公告)号：US20120044772A1

    公开(公告)日：2012-02-23

    申请号：US13114120

    申请日：2011-05-24

    申请人： Chang-Min Jeon ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Ji-Do Ryu

    发明人： Chang-Min Jeon ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Ji-Do Ryu

    IPC分类号： G11C16/10 ,  G11C16/06 ,  G11C16/04

    CPC分类号： G11C16/06 ,  G11C16/0483

    摘要： A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between the first memory cell and the second memory cell, and a second common source line connected between the third memory cell and the fourth memory cell and separated from the first common source line. A first voltage is applied to the first common source line, and a second voltage different from the first voltage is applied to the second common source line.

    摘要翻译： 一种非易失性存储单元阵列，包括由施加到扇区选择线的电压控制的扇区选择晶体管，与扇区选择晶体管串联连接的第一至第四存储器单元，连接在第一存储单元与第二存储单元之间的第一公共源极线 以及连接在第三存储单元和第四存储单元之间并与第一公共源极线分离的第二公共源极线。 向第一公共源极线施加第一电压，并且将不同于第一电压的第二电压施加到第二公共源极线。