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    Semiconductor device and method of fabricating the same
    1.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08592912B2

    公开(公告)日：2013-11-26

    申请号：US13106481

    申请日：2011-05-12

    申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jae-Joo Shim

    发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jae-Joo Shim

    IPC分类号： H01L29/78

    CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

    摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a plurality of conductive patterns stacked on a substrate and spaced apart from each other and a pad pattern including a flat portion extending in a first direction parallel to the substrate from one end of any one of the plurality of conductive patterns, and a landing sidewall portion extending upward from a top surface of the flat portion, wherein a width of a portion of the landing sidewall portion in a second direction parallel to the substrate and perpendicular to the first direction is less than a width of the flat portion.

    摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括：多个导电图案，其堆叠在基板上并彼此间隔开;以及焊盘图案，其包括从多个导电图案中的任一个的一端平行于基板延伸的平坦部分， 以及从所述平坦部分的顶表面向上延伸的着陆侧壁部分，其中所述着陆侧壁部分在平行于所述基板并且垂直于所述第一方向的第二方向上的一部分的宽度小于所述平坦部分的宽度 。

    Three-dimensional semiconductor memory device
    6.
    发明授权
    Three-dimensional semiconductor memory device 有权
    三维半导体存储器件

    公开(公告)号：US08482138B2

    公开(公告)日：2013-07-09

    申请号：US13012485

    申请日：2011-01-24

    申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    IPC分类号： H01L29/40

    CPC分类号： H01L21/768 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

    摘要： Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.

    摘要翻译： 提供一种三维半导体器件及其制造方法。 该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。 第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。 第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。 这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。

    Methods of manufacturing three-dimensional semiconductor devices and related devices
    7.
    发明授权
    Methods of manufacturing three-dimensional semiconductor devices and related devices 有权
    制造三维半导体器件及相关器件的方法

    公开(公告)号：US08394716B2

    公开(公告)日：2013-03-12

    申请号：US12963241

    申请日：2010-12-08

    申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/768 ,  H01L23/5226 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.

    摘要翻译： 三维半导体器件可以包括在基板的布线和接触区域上包括布线和接触区域以及薄膜结构的基板。 薄膜结构可以包括在接触区域中限定梯形结构的多个交替布线层和层间绝缘层，使得每个布线层包括在接触区域中延伸超过其它布线层的接触表面 离衬底更远。 多个接触结构可以在垂直于衬底的表面的方向上延伸，其中每个接触结构电连接到相应的一个接线层的接触表面。 还讨论了相关方法。

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    8.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    三维半导体器件及其制造方法

    公开(公告)号：US20110180941A1

    公开(公告)日：2011-07-28

    申请号：US13012485

    申请日：2011-01-24

    申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    IPC分类号： H01L23/52 ,  H01L21/28

    CPC分类号： H01L21/768 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

    摘要： Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.

    摘要翻译： 提供一种三维半导体器件及其制造方法。 该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。 第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。 第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。 这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。

    Methods of Manufacturing Three-Dimensional Semiconductor Devices and Related Devices
    9.
    发明申请
    Methods of Manufacturing Three-Dimensional Semiconductor Devices and Related Devices 有权
    制造三维半导体器件及相关器件的方法

    公开(公告)号：US20110151667A1

    公开(公告)日：2011-06-23

    申请号：US12963241

    申请日：2010-12-08

    申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    IPC分类号： H01L21/768

    CPC分类号： H01L21/768 ,  H01L23/5226 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.

    摘要翻译： 三维半导体器件可以包括在基板的布线和接触区域上包括布线和接触区域以及薄膜结构的基板。 薄膜结构可以包括在接触区域中限定梯形结构的多个交替布线层和层间绝缘层，使得每个布线层包括在接触区域中延伸超过其它布线层的接触表面 离衬底更远。 多个接触结构可以在垂直于衬底的表面的方向上延伸，其中每个接触结构电连接到相应的一个接线层的接触表面。 还讨论了相关方法。

    Semiconductor device and method of forming the same
    10.
    发明授权
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US08519472B2

    公开(公告)日：2013-08-27

    申请号：US12831728

    申请日：2010-07-07

    申请人： Jaehun Jeong ,  Ju-Young Lim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Jae-Joo Shim

    发明人： Jaehun Jeong ,  Ju-Young Lim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Jae-Joo Shim

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11578 ,  H01L27/11582

    摘要： A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures.

    摘要翻译： 半导体器件包括堆叠栅结构，其包括多个单元栅极图案和交替层叠在半导体衬底上并沿第一方向延伸的绝缘图案。 有源图案和栅极电介质图案设置在堆叠栅极结构中。 有源图案穿透层叠栅极结构并且在与第一方向相交的第二方向上彼此间隔开，并且栅极电介质图案插入在单元栅极图案和有源图案之间并且延伸到第一方向的上表面和下表面 单元格栅格图案。 有源图案共享堆叠栅极结构中的单元栅极图案。