公开(公告)号：US20190279951A1

公开(公告)日：2019-09-12

申请号：US16426365

申请日：2019-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Ping CHIANG ,  Yi-Che CHIANG ,  Nien-Fang WU ,  Min-Chien HSIAO ,  Chao-Wen SHIH ,  Shou-Zen CHANG ,  Chung-Shi LIU ,  Chen-Hua YU

IPC: H01L23/66 ,  H01L23/552 ,  H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

公开(公告)号：US20150228597A1

公开(公告)日：2015-08-13

申请号：US14690570

申请日：2015-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Wen SHIH ,  Yung-Ping CHIANG ,  Chen-Chih HSIEH ,  Hao-Yi TSAI

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/03831 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1369 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/9212 ,  H01L2924/013 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/01029

Abstract: In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure.

Abstract translation: 在形成封装结构的方法中，在半导体衬底上形成金属焊盘，在半导体衬底上形成第一高分子绝缘层。 形成穿过第一聚合物绝缘层的开口以暴露金属垫的一部分。 在第一聚合物绝缘层的开口内和第一聚合物绝缘层上沉积含铜材料，从而在第一聚合物绝缘层上形成具有第一厚度和第一宽度的含铜层。 在含铜层上形成具有第二宽度的导电凸块，其中第二宽度小于第一宽度。 使用导电凸块作为掩模蚀刻含铜层的暴露部分，直到暴露部分被还原成第二厚度，从而形成整体含铜结构。

公开(公告)号：US20180166405A1

公开(公告)日：2018-06-14

申请号：US15625678

申请日：2017-06-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Yung-Ping CHIANG ,  Nien-Fang WU ,  Min-Chien HSIAO ,  Yi-Che CHIANG ,  Chao-Wen SHIH ,  Shou-Zen CHANG ,  Chung-Shi LIU ,  Chen-Hua YU

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/66 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L25/0655 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/24265 ,  H01L2224/25171 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3025 ,  H01L2224/83

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.