公开(公告)号：US09721805B1

公开(公告)日：2017-08-01

申请号：US15223933

申请日：2016-07-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Hui Lee ,  Chen-Wei Pan ,  Yi-Wei Chiu ,  Tzu-Chan Weng

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/265 ,  H01L29/06 ,  H01L21/84

CPC分类号： H01L21/311 ,  H01L21/02129 ,  H01L21/02321 ,  H01L21/02362 ,  H01L21/02579 ,  H01L21/265 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/7851

摘要： Structures and formation methods of a semiconductor device structure are provided. The method includes forming first and second fin structures over a semiconductor substrate. Each of the first and second fin structures has an upper portion and a lower portion. The method also includes forming a phosphosilicate glass (PSG) layer surrounding the upper and lower portions of the first fin structure. The method further includes doping the PSG layer to form a doped PSG layer. In addition, the method includes forming a borosilicate glass (BSG) layer surrounding the upper and lower portions of the second fin structure. The BSG layer extends over the doped PSG layer. The method also includes forming an isolation layer over the BSG layer. The method further includes partially etching the isolation layer, the BSG layer and the doped PSG layer to expose the upper portions of the first and second fin structures.

公开(公告)号：US20220406913A1

公开(公告)日：2022-12-22

申请号：US17824491

申请日：2022-05-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiu-Ling Chen ,  Chih-Teng Liao ,  Jen-Chih Hsueh ,  Chen-Wei Pan ,  Yu-Li Lin

IPC分类号： H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

摘要： Embodiments include methods and devices which utilize dummy gate profiling to provide a profile of a dummy gate which has narrowing in the dummy gate. The narrowing causes a neck in the dummy gate. When the dummy gate is replaced in a gate replacement process, the necking provides control of an etch-back process. Space is provided between the replacement gate and a subsequently formed self-aligned contact.

公开(公告)号：US11824103B2

公开(公告)日：2023-11-21

申请号：US17239225

申请日：2021-04-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chen-Wei Pan ,  Jen-Chih Hsueh ,  Li-Feng Chu ,  Chih-Teng Liao

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/423

CPC分类号： H01L29/66795 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

摘要： In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.