公开(公告)号：US20170125309A1

公开(公告)日：2017-05-04

申请号：US14927816

申请日：2015-10-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yueh-Chuan LEE ,  Chia-Chan CHEN ,  Ping-Chieh CHIN

IPC分类号： H01L21/66 ,  G01R31/28

CPC分类号： H01L22/14 ,  G01R31/2884 ,  H01L22/32 ,  H01L22/34

摘要： Test line structures on a wafer are provided. A first testing pad is formed in a scribe line of the wafer. A second testing pad is formed in the scribe line. A transistor under test is formed in the scribe line and is coupled between the first testing pad and the second testing pad. A device is formed in the scribe line and is coupled between the first testing pad and the transistor under test. A third testing pad is formed in the scribe line and is coupled between the device and the transistor under test. A current passing through the transistor under test is measured via the second testing pad or the first testing pad when a first voltage is applied to the first testing pad, wherein the first voltage is determined according to a second voltage from the third testing pad.

公开(公告)号：US20220367538A1

公开(公告)日：2022-11-17

申请号：US17876438

申请日：2022-07-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yueh-Chuan LEE ,  Shih-Hsien HUANG ,  Chia-Chan CHEN ,  Pu-Fang CHEN

IPC分类号： H01L27/146

摘要： Apparatus and methods for effective impurity gettering are described herein. In some embodiments, a described device includes: a substrate; a pixel region disposed in the substrate; an isolation region disposed in the substrate and within a proximity of the pixel region; and a heterogeneous layer on the seed area. The isolation region comprises a seed area including a first semiconductor material. The heterogeneous layer comprises a second semiconductor material that has a lattice constant different from that of the first semiconductor material.

公开(公告)号：US20190067343A1

公开(公告)日：2019-02-28

申请号：US15690343

申请日：2017-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chia-Chan CHEN ,  Yueh-Chuan LEE ,  Ta-Hsin CHEN ,  Shih-Hsien HUANG ,  Chih-Huang LI

IPC分类号： H01L27/146

CPC分类号： H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689 ,  H01L27/14698

摘要： A photosensor device and the method of making the same are provided. In one embodiment, the device includes at least one pixel cell. The at least one pixel cell includes a substrate formed from a semiconductor material, and includes first and second photosensor regions. The first photosensor region is disposed in the substrate and includes a first dopant of a first conductivity type. The second photosensor region is disposed above the first photosensor region and includes a second dopant of a second conductivity type. The second photosensor region can have an increase in dopant concentration from an outer edge to a center portion therein.

公开(公告)号：US20180166475A1

公开(公告)日：2018-06-14

申请号：US15402836

申请日：2017-01-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Chan CHEN ,  Yueh-Chuan LEE ,  Chih-Huang LI ,  Ta-Hsin CHEN

IPC分类号： H01L27/146

CPC分类号： H01L27/1463 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689

摘要： A method for forming a backside illuminated (BSI) image sensor device structure is provided. The BSI image sensor includes a first substrate having a top surface and a bottom surface, and a plurality of pixel regions formed at the top surface of the first substrate. The BSI image sensor also includes a grid structure through the first substrate and between two adjacent pixel regions. The grid structure extends continuously through the first substrate in a vertical direction and has a top surface and a bottom surface, the top surface of the grid structure protrudes above the bottom surface of the first substrate, and the bottom surface is leveled with the top surface of the first substrate.

公开(公告)号：US20220059582A1

公开(公告)日：2022-02-24

申请号：US16998525

申请日：2020-08-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yueh-Chuan LEE ,  Shih-Hsien HUANG ,  Chia-Chan CHEN ,  Pu-Fang Chen

IPC分类号： H01L27/146

摘要： Apparatus and methods for effective impurity gettering are described herein. In some embodiments, a described device includes: a substrate; a pixel region disposed in the substrate; an isolation region disposed in the substrate and within a proximity of the pixel region; and a heterogeneous layer on the seed area. The isolation region comprises a seed area including a first semiconductor material. The heterogeneous layer comprises a second semiconductor material that has a lattice constant different from that of the first semiconductor material.

公开(公告)号：US20160181213A1

公开(公告)日：2016-06-23

申请号：US14577141

申请日：2014-12-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yueh-Chuan LEE ,  Chia-Chan CHEN

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L21/306 ,  H01L23/58

CPC分类号： H01L24/06 ,  H01L21/30604 ,  H01L21/78 ,  H01L23/585 ,  H01L24/03 ,  H01L24/94 ,  H01L33/0095 ,  H01L2224/05016 ,  H01L2224/06179 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10335 ,  H01L2924/10336 ,  H01L2924/10338 ,  H01L2924/10342 ,  H01L2924/10346 ,  H01L2924/2064

摘要： The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed on a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top surface of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top surface layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the wafer substrate is exposed.

摘要翻译： 半导体管芯包括基体，突出部分和接合焊盘。 基体具有侧壁。 突出部分分别从侧壁侧向突出。 接合焊盘分别设置在突出部分上。 晶片切割方法包括以下操作。 在半导体晶片上形成芯片。 接合焊盘形成在每两个相邻芯片之间的边界线上。 沿着焊盘形成并布置划线。 在半导体晶片的顶表面上形成光刻图案以暴露刻划线。 将划刻线蚀刻到基本上在顶表面层下方的半导体晶片的深度，以形成蚀刻图形。 半导体晶片的背面变薄，直到晶片衬底中的蚀刻图案露出。

公开(公告)号：US20170317043A1

公开(公告)日：2017-11-02

申请号：US15654512

申请日：2017-07-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yueh-Chuan LEE ,  Chia-Chan CHEN

IPC分类号： H01L23/00 ,  H01L23/58 ,  H01L21/306 ,  H01L21/78 ,  H01L33/00

CPC分类号： H01L24/06 ,  H01L21/30604 ,  H01L21/78 ,  H01L23/585 ,  H01L24/03 ,  H01L24/94 ,  H01L33/0095 ,  H01L2224/05016 ,  H01L2224/06179 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10335 ,  H01L2924/10336 ,  H01L2924/10338 ,  H01L2924/10342 ,  H01L2924/10346 ,  H01L2924/2064

摘要： The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed at a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top layer of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the semiconductor wafer is exposed.