-
公开(公告)号：US20180145011A1
公开(公告)日：2018-05-24
申请号：US15801935
申请日：2017-11-02
发明人： Jing-Cheng LIN
IPC分类号： H01L23/48 , H01L21/768 , H01L23/00 , H01L25/065 , H01L25/00 , H01L27/06 , H01L21/762
CPC分类号： H01L23/481 , H01L21/76224 , H01L21/76898 , H01L24/80 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/05025 , H01L2224/05124 , H01L2224/05147 , H01L2224/05563 , H01L2224/05564 , H01L2224/05572 , H01L2224/05573 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/08147 , H01L2224/13 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/80013 , H01L2224/80075 , H01L2224/80091 , H01L2224/80095 , H01L2224/80896 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06524 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/10333 , H01L2924/10335 , H01L2924/10338 , H01L2924/10342 , H01L2224/80 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： Methods for forming a semiconductor device structure are provided. The method includes bonding a first wafer and a second wafer, and a first transistor is formed in a front-side of the first semiconductor wafer. The method further includes thinning a front-side of the second wafer and forming a second transistor in the front-side of the second wafer.
-
公开(公告)号：US09929050B2
公开(公告)日：2018-03-27
申请号：US13943245
申请日：2013-07-16
发明人： Jing-Cheng Lin
IPC分类号： H01L21/768 , H01L23/48 , H01L23/532 , H01L25/065 , H01L23/00 , H01L25/00 , H01L27/06
CPC分类号： H01L21/76898 , H01L21/76849 , H01L23/481 , H01L23/53238 , H01L23/5329 , H01L24/80 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/08147 , H01L2224/80013 , H01L2224/80075 , H01L2224/80091 , H01L2224/80095 , H01L2224/80896 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06524 , H01L2225/06541 , H01L2225/06565 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/10333 , H01L2924/10335 , H01L2924/10338 , H01L2924/10342 , H01L2224/80 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： Embodiments of mechanisms of forming a semiconductor device are provided. The semiconductor device includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconductor wafer. The semiconductor device also includes a second semiconductor wafer comprising a second transistor formed in a front-side of the second semiconductor wafer, and a backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device further includes an first interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer, and the first interconnect structure comprises a first cap metal layer formed over a first conductive feature. The first interconnect structure is electrically connected to first transistor, and the first cap metal layer is configured to prevent diffusion and cracking of the first conductive feature.
-
公开(公告)号：US09748187B2
公开(公告)日：2017-08-29
申请号：US14577141
申请日：2014-12-19
发明人： Yueh-Chuan Lee , Chia-Chan Chen
IPC分类号： H01L23/02 , H01L23/00 , H01L23/58 , H01L21/78 , H01L21/306
CPC分类号： H01L24/06 , H01L21/30604 , H01L21/78 , H01L23/585 , H01L24/03 , H01L24/94 , H01L33/0095 , H01L2224/05016 , H01L2224/06179 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/1033 , H01L2924/10331 , H01L2924/10335 , H01L2924/10336 , H01L2924/10338 , H01L2924/10342 , H01L2924/10346 , H01L2924/2064
摘要： The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed on a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top surface of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top surface layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the wafer substrate is exposed.
-
公开(公告)号：US09530761B2
公开(公告)日：2016-12-27
申请号：US13597973
申请日：2012-08-29
申请人： Alan Roth , Eric Soenen , Chaohao Wang
发明人： Alan Roth , Eric Soenen , Chaohao Wang
CPC分类号： H02M3/158 , H01L23/5226 , H01L24/05 , H01L24/29 , H01L24/45 , H01L24/48 , H01L25/16 , H01L28/10 , H01L28/40 , H01L2224/05025 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/29025 , H01L2224/2919 , H01L2224/32265 , H01L2224/4502 , H01L2224/45111 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48265 , H01L2924/00014 , H01L2924/01047 , H01L2924/0479 , H01L2924/048 , H01L2924/04941 , H01L2924/04953 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/10331 , H01L2924/10332 , H01L2924/10333 , H01L2924/10335 , H01L2924/10337 , H01L2924/10339 , H01L2924/10342 , H01L2924/10351 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/14252 , H01L2924/1427 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H05K1/111 , H05K1/181 , H05K1/185 , H05K2201/10015 , H05K2201/10022 , H05K2201/1003 , H05K2201/10166 , Y02P70/611 , H01L2224/45099 , H01L2924/00
摘要： A package system includes at least one active circuitry disposed over a substrate. A passivation structure is disposed over the at least one active circuitry. The passivation structure has at least one opening that is configured to expose at least one first electrical pad. At least one passive electrical component is disposed over the passivation structure. The at least one passive electrical component is electrically coupled with the at least one first electrical pad.
摘要翻译： 封装系统包括设置在衬底上的至少一个有源电路。 钝化结构设置在至少一个有源电路上。 钝化结构具有至少一个开口，其被配置为暴露至少一个第一电垫。 在钝化结构上方设置至少一个无源电组件。 所述至少一个无源电部件与所述至少一个第一电焊盘电耦合。
-
公开(公告)号：US20160204084A1
公开(公告)日：2016-07-14
申请号：US15076141
申请日：2016-03-21
发明人： Jing-Cheng LIN
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： H01L23/481 , H01L21/76224 , H01L21/76898 , H01L24/80 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/05025 , H01L2224/05124 , H01L2224/05147 , H01L2224/05563 , H01L2224/05564 , H01L2224/05572 , H01L2224/05573 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/08147 , H01L2224/13 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/80013 , H01L2224/80075 , H01L2224/80091 , H01L2224/80095 , H01L2224/80896 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06524 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/10333 , H01L2924/10335 , H01L2924/10338 , H01L2924/10342 , H01L2224/80 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： Methods for forming a semiconductor device structure are provided. The method includes providing a first semiconductor wafer and a second semiconductor wafer. A first transistor is formed in a front-side of the first semiconductor wafer, and no devices are formed in the second semiconductor wafer. The method further includes bonding the front-side of the first semiconductor wafer to a backside of the second semiconductor wafer and thinning a front-side of the second semiconductor wafer. After thinning the second semiconductor wafer, a second transistor is formed in the front-side of the second semiconductor wafer. At least one first through substrate via (TSV) is formed in the second semiconductor wafer, and the first TSV directly contacts a conductive feature of the first semiconductor wafer.
摘要翻译： 提供了形成半导体器件结构的方法。 该方法包括提供第一半导体晶片和第二半导体晶片。 第一晶体管形成在第一半导体晶片的前侧，并且在第二半导体晶片中不形成器件。 该方法还包括将第一半导体晶片的正面接合到第二半导体晶片的背面并使第二半导体晶片的前侧变薄。 在使第二半导体晶片变薄之后，在第二半导体晶片的正面形成第二晶体管。 在第二半导体晶片中形成至少一个第一贯穿衬底通孔（TSV），并且第一TSV直接接触第一半导体晶片的导电特征。
-
公开(公告)号：US20130127037A1
公开(公告)日：2013-05-23
申请号：US13638421
申请日：2011-03-03
申请人： Kentaro Mori , Shintaro Yamamichi , Katsumi Kikuchi , Daisuke Ohshima , Yoshiki Nakashima , Hideya Murai
发明人： Kentaro Mori , Shintaro Yamamichi , Katsumi Kikuchi , Daisuke Ohshima , Yoshiki Nakashima , Hideya Murai
IPC分类号： H01L23/34
CPC分类号： H01L23/34 , H01L23/3114 , H01L23/367 , H01L23/3677 , H01L23/5389 , H01L24/04 , H01L24/12 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L25/0657 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/24146 , H01L2224/32145 , H01L2224/73267 , H01L2225/06589 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10252 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/10342 , H01L2924/12042 , H01L2924/1431 , H01L2924/1432 , H01L2924/1435 , H01L2924/145 , H05K1/0203 , H05K1/185 , H05K2201/10515 , H01L2924/3512 , H01L2924/00
摘要： An object of the present invention is to provide a semiconductor device built-in substrate, which can be made thin and can suppress occurrence of warpage. The present invention provides a semiconductor substrate which is featured by including a first semiconductor device serving as a substrate, a second semiconductor device placed on the circuit surface side of the first semiconductor device in the state where the circuit surfaces of the first and second semiconductor devices are placed to face in the same direction, and an insulating layer incorporating therein the second semiconductor device, and which is featured in that a heat dissipation layer is formed at least between the first semiconductor device and the second semiconductor device, and in that the heat dissipation layer is formed on the first semiconductor device so as to extend up to the outside of the second semiconductor device.
摘要翻译： 本发明的一个目的是提供一种内置半导体器件的基板，它可以制成薄而可以抑制翘曲的发生。 本发明提供一种半导体衬底，其特征在于包括：第一半导体器件，用作衬底;第二半导体器件，其位于第一半导体器件的电路表面侧，处于第一和第二半导体器件的电路表面的状态 被放置成面向相同的方向，并且其中包含第二半导体器件的绝缘层，其特征在于至少在第一半导体器件和第二半导体器件之间形成散热层，并且其中的热量 散热层形成在第一半导体器件上，以便延伸到第二半导体器件的外部。
-
公开(公告)号：US20190027465A1
公开(公告)日：2019-01-24
申请号：US16126428
申请日：2018-09-10
发明人： Sung-Feng Yeh , Chen-Hua Yu , Ming-Fa Chen
IPC分类号： H01L25/065 , H01L21/48 , H01L23/00 , H01L21/56 , H01L23/31 , H01L25/00 , H01L23/522 , H01L23/538 , H01L23/498
CPC分类号： H01L25/0652 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L21/568 , H01L23/3114 , H01L23/3135 , H01L23/315 , H01L23/49816 , H01L23/5226 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/08 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/83 , H01L24/96 , H01L25/50 , H01L2224/04105 , H01L2224/08121 , H01L2224/08145 , H01L2224/12105 , H01L2224/19 , H01L2224/29076 , H01L2224/291 , H01L2224/29186 , H01L2224/32145 , H01L2224/32225 , H01L2224/32227 , H01L2224/73209 , H01L2224/73267 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896 , H01L2224/8203 , H01L2224/83895 , H01L2224/83896 , H01L2224/92124 , H01L2224/97 , H01L2225/06524 , H01L2225/06548 , H01L2225/06555 , H01L2225/06582 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/10331 , H01L2924/10332 , H01L2924/10333 , H01L2924/10335 , H01L2924/10338 , H01L2924/10339 , H01L2924/10342 , H01L2924/14 , H01L2924/141 , H01L2924/143 , H01L2924/1431 , H01L2924/1434 , H01L2924/1816 , H01L2924/18162 , H01L2224/80 , H01L2224/83005 , H01L2224/80001 , H01L2924/00014
摘要： An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.
-
公开(公告)号：US20170317043A1
公开(公告)日：2017-11-02
申请号：US15654512
申请日：2017-07-19
发明人： Yueh-Chuan LEE , Chia-Chan CHEN
IPC分类号： H01L23/00 , H01L23/58 , H01L21/306 , H01L21/78 , H01L33/00
CPC分类号： H01L24/06 , H01L21/30604 , H01L21/78 , H01L23/585 , H01L24/03 , H01L24/94 , H01L33/0095 , H01L2224/05016 , H01L2224/06179 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/1033 , H01L2924/10331 , H01L2924/10335 , H01L2924/10336 , H01L2924/10338 , H01L2924/10342 , H01L2924/10346 , H01L2924/2064
摘要： The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed at a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top layer of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the semiconductor wafer is exposed.
-
公开(公告)号：US20170063236A1
公开(公告)日：2017-03-02
申请号：US15352914
申请日：2016-11-16
发明人： Alan ROTH , Eric SOENEN , Chaohao WANG
CPC分类号： H02M3/158 , H01L23/5226 , H01L24/05 , H01L24/29 , H01L24/45 , H01L24/48 , H01L25/16 , H01L28/10 , H01L28/40 , H01L2224/05025 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/29025 , H01L2224/2919 , H01L2224/32265 , H01L2224/4502 , H01L2224/45111 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48265 , H01L2924/00014 , H01L2924/01047 , H01L2924/0479 , H01L2924/048 , H01L2924/04941 , H01L2924/04953 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/10331 , H01L2924/10332 , H01L2924/10333 , H01L2924/10335 , H01L2924/10337 , H01L2924/10339 , H01L2924/10342 , H01L2924/10351 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/14252 , H01L2924/1427 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H05K1/111 , H05K1/181 , H05K1/185 , H05K2201/10015 , H05K2201/10022 , H05K2201/1003 , H05K2201/10166 , Y02P70/611 , H01L2224/45099 , H01L2924/00
摘要： A converter includes a plurality of active circuitry elements over a substrate. The converter further includes a passivation structure over the plurality of active circuitry elements, the passivation structure having at least one opening that is configured to expose at least one electrical pad of each active circuitry element. The converter further includes a plurality of passive electrical components over the passivation structure, wherein each passive electrical component is selectively connectable with at least one other passive electrical component, and a first side of each passive electrical component is electrically coupled to an electrical pad of each of at least two active circuitry elements. The converter further includes a plurality of electrical connection structures, wherein a first electrical connection structure electrically couples an electrical pad of a first active circuitry element to a corresponding passive electrical component, and the first electrical connection structure is completely within the passivation structure.
摘要翻译： A转换器包括在衬底上的多个有源电路元件。 该转换器还包括多个有源电路元件上的钝化结构，该钝化结构具有至少一个开口，其被配置为暴露每个有源电路元件的至少一个电焊盘。 转换器还包括钝化结构上的多个无源电部件，其中每个无源电部件可选择地与至少一个其它无源电部件连接，并且每个无源电部件的第一侧电耦合到每个无源电部件的电焊盘 至少两个有源电路元件。 转换器还包括多个电连接结构，其中第一电连接结构将第一有源电路元件的电焊盘电耦合到相应的无源电组件，并且第一电连接结构完全在钝化结构内。
-
公开(公告)号：US20160133618A1
公开(公告)日：2016-05-12
申请号：US14995687
申请日：2016-01-14
发明人： CHIA-CHUN MIAO , SHIH-WEI LIANG , KAI-CHIANG WU , YEN-PING WANG
IPC分类号： H01L25/00 , H01L23/00 , H01L25/065
CPC分类号： H01L25/50 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/05011 , H01L2224/05022 , H01L2224/05124 , H01L2224/05572 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05681 , H01L2224/11015 , H01L2224/11334 , H01L2224/11849 , H01L2224/13005 , H01L2224/131 , H01L2224/16145 , H01L2224/16237 , H01L2224/16245 , H01L2224/81007 , H01L2224/8112 , H01L2224/81143 , H01L2224/81191 , H01L2224/81192 , H01L2224/812 , H01L2224/81815 , H01L2224/83007 , H01L2224/83121 , H01L2225/06513 , H01L2225/1058 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/10333 , H01L2924/10335 , H01L2924/10342 , H01L2924/12041 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/2064 , H01L2924/20641 , H01L2924/20642 , H01L2924/3511 , H01L2924/3841 , H01L2924/00 , H01L2924/00014 , H01L2924/00012 , H01L2924/014
摘要： A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer structured metallization and inter-metal dielectric. The integrated circuit is below a passivation, which is over a metal structure. The metal structure includes a metal pad and an under bumper metallurgy, which is over and aligned with the metal pad. The metal pad is electrically connected to the integrated circuit, and the under bumper metallurgy is configured to electrically connect to a conductive component of another semiconductor device. The integrated circuit further includes a conductive trace, which is below and aligned with the metal structure. The conductive trace is connected to a power source such that an electromagnetic field is generated at the conductive trace when an electric current from the power source passes through the conductive trace.
-
-
-
-
-
-
-
-
-
搜索结果
47 条记录 (耗时 0.019 秒)
