公开(公告)号：US09159581B2

公开(公告)日：2015-10-13

申请号：US13686413

申请日：2012-11-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsai-Chun Li ,  Bi-Ming Yen

IPC分类号： H01L21/311 ,  H01L21/768

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816

摘要： This description relates to a method of making a semiconductor device including forming an inter-level dielectric (ILD) layer over a substrate and forming a layer set over the ILD layer. The method further includes etching the layer set to form a tapered opening in the layer set and etching the ILD layer using the layer set as a mask to form an opening in the ILD layer. The opening in the ILD layer has a line width roughness (LWR) of less than 3 nanometers (nm). This description also relates to a semiconductor device including an inter-level dielectric (ILD) layer over a substrate; and a layer set over the ILD layer. The layer set has a tapered opening within the layer set. Etching the layer set comprises forming the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from 85-degrees to 90-degrees.

摘要翻译： 该描述涉及一种制造半导体器件的方法，包括在衬底上形成层间电介质（ILD）层，并在ILD层上形成层。 所述方法还包括蚀刻所述层组以在所述层组中形成锥形开口并使用所述层作为掩模蚀刻所述ILD层，以在所述ILD层中形成开口。 ILD层中的开口具有小于3纳米（nm）的线宽粗糙度（LWR）。 该描述还涉及在衬底上包括层间电介质（ILD）层的半导体器件; 以及设置在ILD层上的层。 层组在层集内具有锥形开口。 蚀刻层组包括形成具有相对于ILD层的顶表面成角度为85度至90度的侧壁的锥形开口。

公开(公告)号：US08853753B2

公开(公告)日：2014-10-07

申请号：US13971267

申请日：2013-08-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/768

CPC分类号： H01L29/78 ,  H01L21/28114 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/823842 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a semiconductor substrate including a source region and a drain region and a gate dielectric over the semiconductor substrate. A metal gate structure is over the semiconductor substrate and the gate dielectric and between the source and drain regions. The integrated circuit further includes an interlayer dielectric (ILD) over the semiconductor substrate. First and second contacts extend through the ILD and adjacent the source and drain regions, respectively, and a third contact extends through the ILD and adjacent a top surface of the metal gate structure. The third contact further extends into an undercut region of the metal gate structure.

摘要翻译： 集成电路包括在半导体衬底上包括源极区和漏极区的半导体衬底和栅极电介质。 金属栅极结构在半导体衬底和栅极电介质之间以及源极和漏极区之间。 集成电路还包括半导体衬底上的层间电介质（ILD）。 第一和第二触点分别延伸穿过ILD并且相邻于源极和漏极区域，并且第三触点延伸穿过ILD并且邻近金属栅极结构的顶表面。 第三触点进一步延伸到金属栅极结构的底切区域。

公开(公告)号：US20130328115A1

公开(公告)日：2013-12-12

申请号：US13971267

申请日：2013-08-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28114 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/823842 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a semiconductor substrate including a source region and a drain region and a gate dielectric over the semiconductor substrate. A metal gate structure is over the semiconductor substrate and the gate dielectric and between the source and drain regions. The integrated circuit further includes an interlayer dielectric (ILD) over the semiconductor substrate. First and second contacts extend through the ILD and adjacent the source and drain regions, respectively, and a third contact extends through the ILD and adjacent a top surface of the metal gate structure. The third contact further extends into an undercut region of the metal gate structure.

摘要翻译： 集成电路包括在半导体衬底上包括源极区和漏极区的半导体衬底和栅极电介质。 金属栅极结构在半导体衬底和栅极电介质之间以及源极和漏极区之间。 集成电路还包括半导体衬底上的层间电介质（ILD）。 第一和第二触点分别延伸穿过ILD并且相邻于源极和漏极区域，并且第三触点延伸穿过ILD并且邻近金属栅极结构的顶表面。 第三触点进一步延伸到金属栅极结构的底切区域。

公开(公告)号：US09589798B2

公开(公告)日：2017-03-07

申请号：US14870428

申请日：2015-09-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsai-Chun Li ,  Bi-Ming Yen

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L21/033

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming a semiconductor device includes forming a dielectric layer over a substrate. The method includes forming a layer set over the dielectric layer, wherein the layer set comprises a plurality of layers. The method further includes forming a bottom antireflective coating (BARC) layer over the layer set. The method further includes etching the layer set to form a tapered opening in the layer set, wherein etching the layer set comprises etching at least one layer comprising a silicon-rich photoresist material layer and a second material layer different from the silicon-rich photoresist material, and the tapered opening has sidewalls at an angle with respect to a top surface of the dielectric layer. The method further includes etching the dielectric layer using the layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a thickness of the layer set.

摘要翻译： 形成半导体器件的方法包括在衬底上形成电介质层。 该方法包括在介电层上形成层，其中层组包括多个层。 该方法还包括在层组上形成底部抗反射涂层（BARC）层。 所述方法还包括蚀刻所述层组以在所述层组中形成锥形开口，其中蚀刻所述层组包括蚀刻至少一层，所述至少一层包括富硅光致抗蚀剂材料层和不同于所述富硅光致抗蚀剂材料的第二材料层 并且锥形开口具有相对于电介质层的顶表面成一定角度的侧壁。 该方法还包括使用设置为掩模的层来蚀刻介电层，以在电介质层中形成开口，其中蚀刻电介质层包括减小层的厚度。

公开(公告)号：US09455156B2

公开(公告)日：2016-09-27

申请号：US14863904

申请日：2015-09-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Bi-Ming Yen ,  Tsai-Chun Li ,  Chun-Ming Hu

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L21/027

CPC分类号： H01L21/31144 ,  H01L21/02118 ,  H01L21/02123 ,  H01L21/0276 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76816

摘要： A method of making a semiconductor device includes forming an intermediate semiconductor device. The intermediate device includes a substrate; and a dielectric layer over the substrate. The intermediate device includes a first layer set, including a silicon-rich photoresist material, over the dielectric layer. The intermediate device includes a second layer set, including a carbon-rich organic material layer, over the first layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set. The method further includes etching the first layer set to form an opening in the first layer set, wherein etching the first layer set comprises removing the carbon-rich organic material layer. The method further includes etching the dielectric layer using the first layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a thickness of the first layer set.

摘要翻译： 制造半导体器件的方法包括形成中间半导体器件。 中间装置包括基板; 以及在该衬底上的电介质层。 中间装置包括在电介质层上的包括富硅光致抗蚀剂材料的第一层组。 中间装置包括在第一层组上的包含富碳的有机材料层的第二层组。 该方法还包括蚀刻第二层组以在第二层组中形成锥形开口。 该方法还包括蚀刻第一层组以在第一层组中形成开口，其中蚀刻第一层组包括去除富含碳的有机材料层。 该方法还包括使用第一层作为掩模来蚀刻介电层，以在电介质层中形成开口，其中蚀刻介电层包括减小第一层组的厚度。

公开(公告)号：US09159580B2

公开(公告)日：2015-10-13

申请号：US13714756

申请日：2012-12-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Bi-Ming Yen ,  Tsai-Chun Li ,  Chun-Ming Hu

IPC分类号： H01L21/311 ,  H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/02118 ,  H01L21/02123 ,  H01L21/0276 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76816

摘要： A mechanism for forming a semiconductor device is described. The semiconductor device includes a substrate and an inter-layer dielectric (ILD) layer over the substrate. The intermediate semiconductor device further includes a first layer set over the ILD layer and a second layer set over the first layer set. The intermediate semiconductor device further includes a photoresist layer over the second layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set, the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from about 85-degrees to about 90-degrees, but less than 90-degrees. The method further includes etching the first layer set to form an opening in the first layer set and etching the ILD layer using the first layer set as a mask to form an opening in the ILD layer.

摘要翻译： 描述了用于形成半导体器件的机构。 半导体器件包括衬底和衬底上的层间电介质（ILD）层。 中间半导体器件还包括设置在ILD层上的第一层和设置在第一层组上的第二层。 中间半导体器件还包括在第二层组上的光致抗蚀剂层。 该方法还包括蚀刻第二层组以在第二层组中形成锥形开口，锥形开口具有相对于ILD层的顶表面成角度约为85度至约90度的侧壁， 但小于90度。 该方法还包括蚀刻第一层组以在第一层组中形成开口，并使用第一层组作为掩模蚀刻ILD层，以在ILD层中形成开口。

公开(公告)号：US20150021672A1

公开(公告)日：2015-01-22

申请号：US14507064

申请日：2014-10-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/42376 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/5283 ,  H01L29/41775 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/785

摘要： An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is first etched to expose a portion of the gate electrode, and then the exposed portion of the gate electrode is etched to form a cavity. The cavity is shaped such that a portion of the gate electrode overhangs the electrode. A conductive material is deposited within the cavity and in electrical contact with the gate electrode. In some such embodiments, the etching of the gate electrode forms a curvilinear surface of the gate electrode that defines the cavity.

摘要翻译： 提供具有改进的栅极接触的集成电路和制造电路的方法。 在示例性实施例中，该方法包括接收衬底。 衬底包括设置在衬底上的栅极堆叠和设置在栅极叠层上的层间电介质。 首先蚀刻层间电介质以暴露栅电极的一部分，然后蚀刻栅极的暴露部分以形成空腔。 空腔成形为使得栅电极的一部分突出于电极。 导电材料沉积在空腔内并与栅电极电接触。 在一些这样的实施例中，栅电极的蚀刻形成限定空腔的栅电极的曲线表面。