公开(公告)号：US11462408B2

公开(公告)日：2022-10-04

申请号：US16881996

申请日：2020-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chun-Hung Lee ,  Yih-Ann Lin ,  De-Fang Chen ,  Chao-Cheng Chen

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3215 ,  H01L21/265 ,  H01L21/027 ,  H01L21/266

摘要： A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

公开(公告)号：US09923079B2

公开(公告)日：2018-03-20

申请号：US15059003

申请日：2016-03-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yuan-Sheng Huang ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang ,  Tzu-Yen Hsieh

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

摘要： A method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a gate layer over the gate dielectric layer, wherein the gate layer is formed in a conformal manner. The method includes forming a dummy gate layer over the gate layer.

公开(公告)号：US20170236712A1

公开(公告)日：2017-08-17

申请号：US15583315

申请日：2017-05-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chun-Hung Lee ,  Yih-Ann Lin ,  De-Fang Chen ,  Chao-Cheng Chen

IPC分类号： H01L21/033 ,  H01L21/265 ,  H01L21/266 ,  H01L21/027

CPC分类号： H01L21/0338 ,  H01L21/0276 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/32155

摘要： A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

公开(公告)号：US09276089B2

公开(公告)日：2016-03-01

申请号：US14815492

申请日：2015-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu Chao Lin ,  Tzu-Yen Hsieh ,  Ming-Chia Tai ,  Chao-Cheng Chen

IPC分类号： H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3105

CPC分类号： H01L29/66795 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/31051 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/6656

摘要： Methods for forming a semiconductor device and a FinFET device are disclosed. A method comprises forming a dummy gate electrode layer over a substrate, the dummy gate electrode layer having a first height, forming a first etch stop layer on the dummy gate electrode layer, forming a first hard mask layer on the first etch stop layer, and patterning the first hard mask layer. The method further comprises patterning the first etch stop layer to align with the patterned first hard mask layer, and patterning the gate electrode layer to form a dummy gate electrode, the dummy gate electrode aligning with the patterned first etch stop layer, wherein after the patterning the gate electrode layer the first hard mask layer has a vertical sidewall of a second height, the second height being less than the first height, and the first hard mask layer having a rounded top surface.

公开(公告)号：US20220375752A1

公开(公告)日：2022-11-24

申请号：US17883406

申请日：2022-08-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chun-Hung Lee ,  Yih-Ann Lin ,  De-Fang Chen ,  Chao-Cheng Chen

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3215

摘要： A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

公开(公告)号：US09640398B2

公开(公告)日：2017-05-02

申请号：US14711842

申请日：2015-05-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chun-Hung Lee ,  Yih-Ann Lin ,  De-Fang Chen ,  Chao-Cheng Chen

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3215 ,  H01L21/265 ,  H01L21/027 ,  H01L21/266

CPC分类号： H01L21/0338 ,  H01L21/0276 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/32155

摘要： A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

公开(公告)号：US20140256094A1

公开(公告)日：2014-09-11

申请号：US13790742

申请日：2013-03-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chao Lin ,  Tzu-Yen Hsieh ,  Ming-Chia Tai ,  Chao-Cheng Chen

IPC分类号： H01L29/66

CPC分类号： H01L29/66795 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/31051 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/6656

摘要： Methods for forming a semiconductor device and a FinFET device are disclosed. A method comprises forming a dummy gate electrode layer over a substrate, the dummy gate electrode layer having a first height, forming a first etch stop layer on the dummy gate electrode layer, forming a first hard mask layer on the first etch stop layer, and patterning the first hard mask layer. The method further comprises patterning the first etch stop layer to align with the patterned first hard mask layer, and patterning the gate electrode layer to form a dummy gate electrode, the dummy gate electrode aligning with the patterned first etch stop layer, wherein after the patterning the gate electrode layer the first hard mask layer has a vertical sidewall of a second height, the second height being less than the first height, and the first hard mask layer having a rounded top surface.

摘要翻译： 公开了形成半导体器件和FinFET器件的方法。 一种方法包括在衬底上形成伪栅极电极层，所述虚拟栅极电极层具有第一高度，在所述伪栅电极层上形成第一蚀刻停止层，在所述第一蚀刻停止层上形成第一硬掩模层，以及 图案化第一硬掩模层。 该方法还包括使第一蚀刻停止层图案化以与图案化的第一硬掩模层对准，以及图案化栅极电极层以形成伪栅电极，虚拟栅电极与图案化的第一蚀刻停止层对准，其中在图案化之后 第一硬掩模层的栅电极层具有第二高度的垂直侧壁，第二高度小于第一高度，并且第一硬掩模层具有圆形顶表面。

公开(公告)号：US20200312663A1

公开(公告)日：2020-10-01

申请号：US16881996

申请日：2020-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chun-Hung Lee ,  Yi-Ann Lin ,  De-Fang Chen ,  Chao-Cheng Chen

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3215 ,  H01L21/265 ,  H01L21/027 ,  H01L21/266

摘要： A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

公开(公告)号：US10269581B2

公开(公告)日：2019-04-23

申请号：US15722405

申请日：2017-10-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chia-Wei Chang ,  Chao-Cheng Chen ,  Chun-Hung Lee ,  Dai-Lin Wu

IPC分类号： H01L21/3215 ,  H01L21/3213 ,  H01L21/266 ,  H01L21/033 ,  H01L21/28 ,  H01L21/265

摘要： A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas.

公开(公告)号：US09779963B2

公开(公告)日：2017-10-03

申请号：US14813189

申请日：2015-07-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chia-Wei Chang ,  Chao-Cheng Chen ,  Chun-Hung Lee ,  Dai-Lin Wu

IPC分类号： H01L21/266 ,  H01L21/3215 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/265

CPC分类号： H01L21/3215 ,  H01L21/0338 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/32134 ,  H01L21/32139

摘要： A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas.