公开(公告)号：US20240194523A1

公开(公告)日：2024-06-13

申请号：US18582746

申请日：2024-02-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L27/092

CPC分类号： H01L21/76831 ,  H01L21/76813 ,  H01L23/5226 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7684 ,  H01L27/092

摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an interconnect dielectric layer over a substrate. An interconnect via is within the interconnect dielectric layer, and an interconnect wire is over the interconnect via and within the interconnect dielectric layer. A protective layer surrounds the interconnect via. The interconnect via vertically extends through the protective layer to below a bottom of the protective layer. The protective layer continuously extends from along an outer sidewall of the interconnect via to along an outer sidewall of the interconnect wire in a first cross-sectional view.

公开(公告)号：US11854965B2

公开(公告)日：2023-12-26

申请号：US17834204

申请日：2022-06-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Teng Dai ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Hsi-Wen Tien ,  Wei-Hao Liao

IPC分类号： H01L21/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76829 ,  H01L23/528 ,  H01L23/53295

摘要： Some embodiments relate to a method for forming a semiconductor structure, the method includes forming a first dielectric layer over a substrate. A first conductive wire is formed over the first dielectric layer. A spacer structure is formed over the first conductive wire. The spacer structure is disposed along sidewalls of the first conductive wire. A second dielectric layer is deposited over and around the first conductive wire. The spacer structure is spaced between the first conductive wire and the second dielectric layer. A removal process is performed on the spacer structure and the second dielectric layer. An upper surface of the spacer structure is disposed above an upper surface of the first conductive wire.

公开(公告)号：US20230369231A1

公开(公告)日：2023-11-16

申请号：US18360066

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  Yu-Teng Dai ,  Hsin-Yen Huang ,  Chia-Tien Wu

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/532

CPC分类号： H01L23/5384 ,  H01L21/76802 ,  H01L21/486 ,  H01L23/5386 ,  H01L21/7682 ,  H01L23/5329

摘要： The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.

公开(公告)号：US20230275028A1

公开(公告)日：2023-08-31

申请号：US18311308

申请日：2023-05-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L23/535 ,  H01L21/76895 ,  H01L21/76805 ,  H01L21/76802

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

公开(公告)号：US11728271B2

公开(公告)日：2023-08-15

申请号：US17080051

申请日：2020-10-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Tien-I Bao

IPC分类号： H01L23/52 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/485

CPC分类号： H01L23/535 ,  H01L21/31144 ,  H01L21/7682 ,  H01L23/528 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L21/76807 ,  H01L21/76885 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region.

公开(公告)号：US20220359368A1

公开(公告)日：2022-11-10

申请号：US17313217

申请日：2021-05-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Hao Liao ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Chung-Ju Lee

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/768

摘要： An interconnect structure includes dielectric layer, a first conductive feature, a second conductive feature, a third conductive feature, and a dielectric fill. The first conductive feature is disposed in the dielectric layer. The second conductive feature is disposed over the first conductive feature. The second conductive feature includes a first conductive layer disposed over the first conductive feature, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The first conductive layer, the second conductive layer and the third conductive layer have substantially the same width. The third conductive feature is disposed over the dielectric layer. The dielectric fill is disposed over the dielectric layer between the second conductive feature and the third conductive feature.

公开(公告)号：US20220336263A1

公开(公告)日：2022-10-20

申请号：US17855060

申请日：2022-06-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/8234

摘要： The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

公开(公告)号：US20220059404A1

公开(公告)日：2022-02-24

申请号：US17518885

申请日：2021-11-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

摘要： Some embodiments relate to a semiconductor device disposed on a semiconductor substrate. A dielectric structure is arranged over the semiconductor substrate. First and second metal vias are disposed in the dielectric structure and spaced laterally apart from one another. First and second metal lines are disposed in the dielectric structure and have nearest neighboring sidewalls that are spaced laterally apart from one another by a portion of the dielectric structure. The first and second metal lines contact upper portions of the first and second metal vias, respectively. First and second air gaps are disposed in the portion of the dielectric structure. The first and second air gaps are proximate to nearest neighboring sidewalls of the first and second metal lines, respectively.

公开(公告)号：US20190252249A1

公开(公告)日：2019-08-15

申请号：US16390715

申请日：2019-04-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Hsu Wu ,  Chien-Hua Huang ,  Chung-Ju Lee ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522

摘要： A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.

公开(公告)号：US10312139B2

公开(公告)日：2019-06-04

申请号：US15626839

申请日：2017-06-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Shau-Lin Shue ,  Tien-I Bao

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528

摘要： A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the first dielectric layer. The structure further includes an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and the etch stop layer provide a via hole that partially exposes the conductive line. The structure further includes a via disposed in the via hole, and another conductive line disposed over the via and coupled to the conductive line through the via. Methods of forming the multilayer interconnect structure are also disclosed. The etch stop layer reduces the lateral and vertical etching of the first and second dielectric layers when the via hole is misaligned due to overlay errors.