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    Thermal interface material system
    1.
    发明授权
    Thermal interface material system 有权

    公开(公告)号：US11060805B2

    公开(公告)日：2021-07-13

    申请号：US14967087

    申请日：2015-12-11

    申请人： TELEDYNE SCIENTIFIC & IMAGING, LLC.

    发明人： Tadej Semenic ,  Kyle D. Gould ,  Avijit Bhunia

    IPC分类号： H01L23/373 ,  F28F21/08 ,  F28F13/00 ,  H01L23/42 ,  F28F21/02

    摘要： A thermal interface material system includes a thermally conductive porous matrix, the thermally conductive porous matrix having a plurality of interstitial voids, and a thermally conductive colloidal suspension disposed on each side of the thermally conductive porous matrix to inhibit thermal pump-out of the thermally conductive colloidal suspension so that the thermally conductive porous matrix and thermally conductive colloidal suspension collectively form a thermally conductive porous pad.

    FET WITH MICRO-SCALE DEVICE ARRAY
    5.
    发明申请
    FET WITH MICRO-SCALE DEVICE ARRAY 审中-公开

    公开(公告)号：US20190006464A1

    公开(公告)日：2019-01-03

    申请号：US15638041

    申请日：2017-06-29

    申请人： Teledyne Scientific & Imaging, LLC

    发明人： Keisuke Shinohara ,  Miguel Urteaga ,  Casey King ,  Avijit Bhunia ,  Ya-Chi Chen

    IPC分类号： H01L29/06 ,  H01L29/778 ,  H01L29/20 ,  H01L29/423

    摘要： A FET employing a micro-scale device array structure comprises a substrate on which an epitaxial active channel area has been grown, with a plurality of micro-cells uniformly distributed over the active channel area. Each micro-cell comprises a source electrode, a drain electrode, and at least one gate electrode, with a first metal layer interconnecting either the drain or the source electrodes, a second metal layer interconnecting the gate electrodes, and a third metal layer interconnecting the other of the drain or source electrodes. Each micro-cell preferably comprises a source or drain electrode at the center of the micro-cell, with the corresponding drain or source electrode surrounding the center electrode. The number and width of the gate electrodes in each micro-cell may be selected to achieve a desired power density and/or heat distribution, and/or to minimize the FET's junction temperature. The FET structure may be used to form, for example, HEMTs or MESFETs.

    OSCILLATION MINI-CHANNEL COOKWARE
    6.
    发明申请
    OSCILLATION MINI-CHANNEL COOKWARE 审中-公开

    公开(公告)号：US20170208984A1

    公开(公告)日：2017-07-27

    申请号：US15004527

    申请日：2016-01-22

    申请人： TELEDYNE SCIENTIFIC & IMAGING, LLC

    发明人： Steve Cai ,  Avijit Bhunia

    IPC分类号： A47J27/02 ,  A47J36/02

    CPC分类号： A47J27/02 ,  A47J27/026 ,  A47J36/02

    摘要： Cookware such as griddles and pots are formed with an oscillation mini-channel that winds back-and-forth between direct and indirect heating regions. An operating fluid that occupies 30-90 percent of the volume of the oscillation mini-channel is placed under vacuum. The mini-channel is dimensioned to produce capillary forces that create vapor bubbles and liquid slugs interspersed throughout the oscillation mini-channel. Heating of the direct heating region creates oscillatory movements of the vapor bubbles and liquid slugs that transfers heat from the direct heating region to the indirect heating region to maintain a more uniform temperature across the food-heating zone. The cookware may exhibit an effective thermal conductivity of at least 1,000 W/m·K.

    FET with micro-scale device array
    7.
    发明授权
    FET with micro-scale device array 有权

    公开(公告)号：US10249711B2

    公开(公告)日：2019-04-02

    申请号：US15638041

    申请日：2017-06-29

    申请人： Teledyne Scientific & Imaging, LLC

    发明人： Keisuke Shinohara ,  Miguel Urteaga ,  Casey King ,  Avijit Bhunia ,  Ya-Chi Chen

    IPC分类号： H01L29/15 ,  H01L29/66 ,  H01L27/088 ,  H01L21/337 ,  H01L29/06 ,  H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/417 ,  H01L23/522

    摘要： A FET employing a micro-scale device array structure comprises a substrate on which an epitaxial active channel area has been grown, with a plurality of micro-cells uniformly distributed over the active channel area. Each micro-cell comprises a source electrode, a drain electrode, and at least one gate electrode, with a first metal layer interconnecting either the drain or the source electrodes, a second metal layer interconnecting the gate electrodes, and a third metal layer interconnecting the other of the drain or source electrodes. Each micro-cell preferably comprises a source or drain electrode at the center of the micro-cell, with the corresponding drain or source electrode surrounding the center electrode. The number and width of the gate electrodes in each micro-cell may be selected to achieve a desired power density and/or heat distribution, and/or to minimize the FET's junction temperature. The FET structure may be used to form, for example, HEMTs or MESFETs.

    Interface-Free Thermal Management System for High Power Devices Co-Fabricated with Electronic Circuit
    8.
    发明申请
    Interface-Free Thermal Management System for High Power Devices Co-Fabricated with Electronic Circuit 审中-公开

    公开(公告)号：US20190086162A1

    公开(公告)日：2019-03-21

    申请号：US16194690

    申请日：2018-11-19

    申请人： TELEDYNE SCIENTIFIC & IMAGING, LLC

    发明人： Steve Q. Cai ,  Avijit Bhunia ,  Tadej Semenic

    IPC分类号： F28F3/04 ,  H01L23/427 ,  F28D15/04

    摘要： A thermal-interface-material (TIM)-free thermal management apparatus includes a thermally-conductive unitary structure having an integrated circuit (IC) side and cooling system side, the thermally-conductive unitary structure including a plurality of high aspect ratio micro-pillars or porous structures extending from the IC side and a cooling system extending from the cooling system side. The cooling system may be selected from the group consisting of: a vapor chamber, micro-channel cooler, jet-impingement chamber, and air-cooled heat sink. The cooling system and the plurality of high aspect ratio micro-pillars form part of the same homogenous and thermally-conductive unitary structure.