公开(公告)号：US09054158B2

公开(公告)日：2015-06-09

申请号：US13762529

申请日：2013-02-08

Applicant: Texas Instruments Incorporated

Inventor： David Gerald Farber ,  Tom Lii ,  Steve Lytle

IPC: H01L21/00 ,  H01L21/768

CPC classification number: H01L21/76804 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

Abstract: The width of a metal contact opening is formed to be smaller than the minimum feature size of a photolithographically-defined opening. The method forms the metal contact opening by first etching the fourth layer of a multilayered hard mask structure to have a number of trenches that expose the third layer of the multilayered hard mask structure. Following this, the third, second, and first layers of the multilayered hard mask structure are selectively etched to expose uncovered regions on the top surface of an isolation layer that touches and lies over a source region and a drain region. The uncovered regions on the top surface of the isolation layer are then etched to form the metal contact openings.

Abstract translation: 金属接触开口的宽度形成为小于光刻限定开口的最小特征尺寸。 该方法通过首先蚀刻多层硬掩模结构的第四层来形成金属接触开口，以具有暴露多层硬掩模结构的第三层的多个沟槽。 接下来，选择性地蚀刻多层硬掩模结构的第三层，第二层和第一层，以暴露接触并位于源极区域和漏极区域上的隔离层的顶表面上的未覆盖区域。 然后蚀刻隔离层的顶表面上的未覆盖区域以形成金属接触开口。

公开(公告)号：US09881795B2

公开(公告)日：2018-01-30

申请号：US15287889

申请日：2016-10-07

Applicant: Texas Instruments Incorporated

Inventor： David Gerald Farber ,  Ping Jiang ,  Brian K. Kirkpatrick ,  Douglas T. Grider, III

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L21/8234

CPC classification number: H01L21/28123 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462

Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

公开(公告)号：US09490143B1

公开(公告)日：2016-11-08

申请号：US14952693

申请日：2015-11-25

Applicant: Texas Instruments Incorporated

Inventor： David Gerald Farber ,  Ping Jiang ,  Brian K. Kirkpatrick ,  Douglas T. Grider, III

IPC: H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L21/28123 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462

Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

Abstract translation: 制造半导体的方法包括将平坦化材料施加到基板并在平坦化材料中形成开口。 开口充满了多晶硅。 多个蚀刻调制序列被施加到衬底，每个蚀刻调制序列包括：对衬底施加第一蚀刻工艺，其中第一蚀刻工艺比平坦化材料对多晶硅更有选择性; 以及对所述衬底施加第二蚀刻工艺，其中所述第二蚀刻工艺对所述平坦化材料比所述多晶硅更具选择性。

公开(公告)号：US09224657B2

公开(公告)日：2015-12-29

申请号：US13960517

申请日：2013-08-06

Applicant: Texas Instruments Incorporated

Inventor： David Gerald Farber ,  Tom Lii ,  Brian K. Kirkpatrick

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807

Abstract: An integrated circuit is formed to include a first polarity MOS transistor and a second, opposite, polarity MOS transistor. A hard mask of silicon-doped boron nitride (SixBN) with 1 atomic percent to 30 atomic percent silicon is formed over the first polarity MOS transistor and the second polarity MOS transistor. The hard mask is removed from source/drain regions of the first polarity MOS transistor and left in place over the second polarity MOS transistor. Semiconductor material is epitaxially grown at the source/drain regions of the first polarity MOS transistor while the hard mask is in place. Subsequently, the hard mask is removed from the second polarity MOS transistor.

Abstract translation: 集成电路形成为包括第一极性MOS晶体管和第二相反极性MOS晶体管。 在第一极性MOS晶体管和第二极性MOS晶体管上形成具有1原子％至30原子％硅的硅掺杂氮化硼（SixBN）的硬掩模。 硬掩模从第一极性MOS晶体管的源极/漏极区域移除，并且在第二极性MOS晶体管上保持原位。 半导体材料在第一极性MOS晶体管的源极/漏极区域外延生长，同时硬掩模就位。 随后，从第二极性MOS晶体管去除硬掩模。

公开(公告)号：US20150044830A1

公开(公告)日：2015-02-12

申请号：US13960517

申请日：2013-08-06

Applicant: Texas Instruments Incorporated

Inventor： David Gerald Farber ,  Tom Lii ,  Brian K. Kirkpatrick

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807

Abstract: An integrated circuit is formed to include a first polarity MOS transistor and a second, opposite, polarity MOS transistor. A hard mask of silicon-doped boron nitride (SixBN) with 1 atomic percent to 30 atomic percent silicon is formed over the first polarity MOS transistor and the second polarity MOS transistor. The hard mask is removed from source/drain regions of the first polarity MOS transistor and left in place over the second polarity MOS transistor. Semiconductor material is epitaxially grown at the source/drain regions of the first polarity MOS transistor while the hard mask is in place. Subsequently, the hard mask is removed from the second polarity MOS transistor.

Abstract translation: 集成电路形成为包括第一极性MOS晶体管和第二相反极性MOS晶体管。 在第一极性MOS晶体管和第二极性MOS晶体管上形成具有1原子％至30原子％硅的硅掺杂氮化硼（SixBN）的硬掩模。 硬掩模从第一极性MOS晶体管的源极/漏极区域移除，并且在第二极性MOS晶体管上保持原位。 半导体材料在第一极性MOS晶体管的源极/漏极区域外延生长，同时硬掩模就位。 随后，从第二极性MOS晶体管去除硬掩模。

公开(公告)号：US20140227877A1

公开(公告)日：2014-08-14

申请号：US13762529

申请日：2013-02-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David Gerald Farber ,  Tom Lii ,  Steve Lytle

IPC: H01L21/768

CPC classification number: H01L21/76804 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

Abstract: The width of a metal contact opening is formed to be smaller than the minimum feature size of a photolithographically-defined opening. The method forms the metal contact opening by first etching the fourth layer of a multilayered hard mask structure to have a number of trenches that expose the third layer of the multilayered hard mask structure. Following this, the third, second, and first layers of the multilayered hard mask structure are selectively etched to expose uncovered regions on the top surface of an isolation layer that touches and lies over a source region and a drain region. The uncovered regions on the top surface of the isolation layer are then etched to form the metal contact openings.

Abstract translation: 金属接触开口的宽度形成为小于光刻限定开口的最小特征尺寸。 该方法通过首先蚀刻多层硬掩模结构的第四层来形成金属接触开口，以具有暴露多层硬掩模结构的第三层的多个沟槽。 接下来，选择性地蚀刻多层硬掩模结构的第三层，第二层和第一层，以暴露接触并位于源极区域和漏极区域上的隔离层的顶表面上的未覆盖区域。 然后蚀刻隔离层的顶表面上的未覆盖区域以形成金属接触开口。

公开(公告)号：US10453700B2

公开(公告)日：2019-10-22

申请号：US14973973

申请日：2015-12-18

Applicant: Texas Instruments Incorporated

Inventor： Ping Jiang ,  David Gerald Farber

IPC: H01L21/311 ,  H01L21/3105 ,  H01L21/768

Abstract: A method of forming an interconnect structure for an integrated circuit. A dielectric stack is formed on the substrate including an etch-stop layer, a low-k or ULK dielectric layer, and a hard mask layer. The low-k or ULK dielectric is etched using at least two etching processes wherein each etching process is followed by an etch repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma. The photoresist may be removed using at least two ashing processes wherein each ashing process is followed by an ash repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma.

公开(公告)号：US20170148634A1

公开(公告)日：2017-05-25

申请号：US15287889

申请日：2016-10-07

Applicant: Texas Instruments Incorporated

Inventor： David Gerald Farber ,  Ping Jiang ,  Brian K. Kirkpatrick ,  Douglas T. Grider, III

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/28123 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462

Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.