公开(公告)号：US20240364276A1

公开(公告)日：2024-10-31

申请号：US18648037

申请日：2024-04-26

Applicant: Texas Instruments Incorporated

Inventor： Chandrasekhar Sriram ,  Sarma Sundareswara Gunturi ,  Jawaharlal Tangudu ,  Harshit Moondra ,  Harsh Garg ,  Sanjay Pennam

IPC: H03F1/32 ,  H03F3/24

CPC classification number: H03F1/3241 ,  H03F3/245 ,  H03F2200/451

Abstract: Methods, apparatus, systems, and articles of manufacture are described for dynamic digital pre-distortion correction. An example system includes programmable circuitry operable to execute computer readable instructions to at least: generate signal statistics based on an input signal; group the signal statistics into a first group of signal statistics or a second group of signal statistics based on time constants of the signal statistics; decimate the first group of signal statistics; generate a first predistortion term based on the decimated first group of signal statistics; generate a second predistortion term based on the second group of signal statistics; and generate an output predistortion terminal based on the first predistortion term and the second predistortion term.

公开(公告)号：US12074607B2

公开(公告)日：2024-08-27

申请号：US17825864

申请日：2022-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Nithin Gopinath ,  Viswanathan Nagarajan ,  Neeraj Shrivastava ,  Visvesvaraya A. Pentakota ,  Harshit Moondra ,  Abhinav Chandra

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

公开(公告)号：US11881867B2

公开(公告)日：2024-01-23

申请号：US17467561

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Eeshan Miglani ,  Chirag Chandrahas Shetty ,  Neeraj Shrivastava ,  Shagun Dusad ,  Srinivas Kumar Reddy Naru ,  Nithin Gopinath ,  Charls Babu ,  Shivam Srivastava ,  Viswanathan Nagarajan ,  Jagannathan Venkataraman ,  Harshit Moondra ,  Prasanth K ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

CPC classification number: H03M1/1019

Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

公开(公告)号：US20230344436A1

公开(公告)日：2023-10-26

申请号：US17729374

申请日：2022-04-26

Applicant: Texas Instruments Incorporated

Inventor： Nithin Gopinath ,  Visvesvaraya A. Pentakota ,  Neeraj Shrivastava ,  Harshit Moondra

IPC: H03M1/06

CPC classification number: H03M1/0641 ,  H03M1/0626

Abstract: An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.

公开(公告)号：US12224761B2

公开(公告)日：2025-02-11

申请号：US17729374

申请日：2022-04-26

Applicant: Texas Instruments Incorporated

Inventor： Nithin Gopinath ,  Visvesvaraya A. Pentakota ,  Neeraj Shrivastava ,  Harshit Moondra

IPC: H03M1/20 ,  H03M1/06

Abstract: An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.

公开(公告)号：US20220247420A1

公开(公告)日：2022-08-04

申请号：US17467561

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Eeshan Miglani ,  Chirag Chandrahas Shetty ,  Neeraj Shrivastava ,  Shagun Dusad ,  Srinivas Kumar Reddy Naru ,  Nithin Gopinath ,  Charls Babu ,  Shivam Srivastava ,  Viswanathan Nagarajan ,  Jagannathan Venkataraman ,  Harshit Moondra ,  Prasanth K ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.