中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.013 seconds)

    Noise-Shaping of Additive Dither in Analog-to-Digital Converters
    1.
    发明公开
    Noise-Shaping of Additive Dither in Analog-to-Digital Converters 审中-公开

    公开(公告)号：US20230344436A1

    公开(公告)日：2023-10-26

    申请号：US17729374

    申请日：2022-04-26

    Applicant: Texas Instruments Incorporated

    Inventor： Nithin Gopinath ,  Visvesvaraya A. Pentakota ,  Neeraj Shrivastava ,  Harshit Moondra

    IPC: H03M1/06

    CPC classification number: H03M1/0641 ,  H03M1/0626

    Abstract: An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.

    CALIBRATION SCHEME FOR A NON-LINEAR ADC
    2.
    发明申请
    CALIBRATION SCHEME FOR A NON-LINEAR ADC 有权

    公开(公告)号：US20220224349A1

    公开(公告)日：2022-07-14

    申请号：US17568972

    申请日：2022-01-05

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Himanshu Varshney ,  Viswanathan Nagarajan ,  Charls Babu ,  Narasimhan Rajagopal ,  Eeshan Miglani ,  Visvesvaraya A. Pentakota

    IPC: H03M1/10

    Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

    PIPELINE ADC AND REFERENCE LOAD BALANCING CIRCUIT AND METHOD TO BALANCE REFERENCE CIRCUIT LOAD
    4.
    发明申请
    PIPELINE ADC AND REFERENCE LOAD BALANCING CIRCUIT AND METHOD TO BALANCE REFERENCE CIRCUIT LOAD 有权
    管道ADC和参考负载平衡电路以及平衡参考电路负载的方法

    公开(公告)号：US20160072518A1

    公开(公告)日：2016-03-10

    申请号：US14848499

    申请日：2015-09-09

    Applicant: Texas Instruments Incorporated

    Inventor： Roswald Francis ,  Visvesvaraya A. Pentakota

    IPC: H03M1/46 ,  H03M1/00 ,  H03M1/06 ,  H03M1/44

    CPC classification number: H03M1/0604 ,  H03M1/00 ,  H03M1/002 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/167 ,  H03M1/361 ,  H03M1/44 ,  H03M1/468

    Abstract: Disclosed examples include pipeline ADC, balancing circuits and methods to balance a load of a reference circuit to reduce non-linearity and settling effects for a reference voltage signal, in which balancing capacitors are connected to a voltage source in a pipeline stage ADC sample time period to precharge the balancing capacitors using a voltage above the reference voltage, and a selected set of the precharged balancing capacitors is connected to provide charge to the output of the reference circuit during the second time period.

    Abstract translation: 公开的示例包括流水线ADC，平衡电路和平衡参考电路的负载以减少参考电压信号的非线性和稳定效应的方法，其中平衡电容器连接到流水线级ADC采样时间段中的电压源 使用高于参考电压的电压对平衡电容器进行预充电，并且连接一组选定的预充电平衡电容器，以在第二时间段期间向参考电路的输出提供电荷。

    Noise-shaping of additive dither in analog-to-digital converters
    6.
    发明授权
    Noise-shaping of additive dither in analog-to-digital converters 有权

    公开(公告)号：US12224761B2

    公开(公告)日：2025-02-11

    申请号：US17729374

    申请日：2022-04-26

    Applicant: Texas Instruments Incorporated

    Inventor： Nithin Gopinath ,  Visvesvaraya A. Pentakota ,  Neeraj Shrivastava ,  Harshit Moondra

    IPC: H03M1/20 ,  H03M1/06

    Abstract: An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.

Patent Agency Ranking