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公开(公告)号：US20230054834A1
公开(公告)日：2023-02-23
申请号：US17567775
申请日：2022-01-03
Applicant: Texas Instruments Incorporated
Inventor： Rakesh Manjunath , Aravind Ganesan , Ani Xavier , Jagannathan Venkataraman , Abhishek Agrawal , Charls Babu , Aditya Kumar
Abstract: A signal transmission system includes an equalization filter configured to filter an input signal based at least in part on a feedback signal, a slicer configured to generate data based on the filtered input signal at a plurality of different phases, a synchronizer configured to compute a phase delay between the input signal at each of the different phases and the data, and a pattern generator configured to generate the feedback signal at a phase adjusted by the phase delay.
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公开(公告)号：US12166500B2
公开(公告)日：2024-12-10
申请号：US18461152
申请日：2023-09-05
Applicant: Texas Instruments Incorporated
Inventor： Nagarajan Viswanathan , Himanshu Varshney , Vinam Arora , Charls Babu , Srinivas Kumar Naru
Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.
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公开(公告)号：US11855816B2
公开(公告)日：2023-12-26
申请号：US17567775
申请日：2022-01-03
Applicant: Texas Instruments Incorporated
Inventor： Rakesh Manjunath , Aravind Ganesan , Ani Xavier , Jagannathan Venkataraman , Abhishek Agrawal , Charls Babu , Aditya Kumar
Abstract: A signal transmission system includes an equalization filter configured to filter an input signal based at least in part on a feedback signal, a slicer configured to generate data based on the filtered input signal at a plurality of different phases, a synchronizer configured to compute a phase delay between the input signal at each of the different phases and the data, and a pattern generator configured to generate the feedback signal at a phase adjusted by the phase delay.
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公开(公告)号：US20240187013A1
公开(公告)日：2024-06-06
申请号：US18440113
申请日：2024-02-13
Applicant: Texas Instruments Incorporated
Inventor： Himanshu Varshney , Viswanathan Nagarajan , Charls Babu , Narasimhan Rajagopal , Eeshan Miglani , Visvesvaraya A. Pentakota
CPC classification number: H03M1/1009 , H03M1/002 , H03M1/10 , H03M1/12
Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.
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Patent Agency Ranking
公开(公告)号：US11962318B2
公开(公告)日：2024-04-16
申请号：US17568972
申请日：2022-01-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Himanshu Varshney , Viswanathan Nagarajan , Charls Babu , Narasimhan Rajagopal , Eeshan Miglani , Visvesvaraya A Pentakota
CPC classification number: H03M1/1009 , H03M1/002 , H03M1/10 , H03M1/12
Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.
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公开(公告)号：US11881867B2
公开(公告)日：2024-01-23
申请号：US17467561
申请日：2021-09-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Narasimhan Rajagopal , Eeshan Miglani , Chirag Chandrahas Shetty , Neeraj Shrivastava , Shagun Dusad , Srinivas Kumar Reddy Naru , Nithin Gopinath , Charls Babu , Shivam Srivastava , Viswanathan Nagarajan , Jagannathan Venkataraman , Harshit Moondra , Prasanth K , Visvesvaraya Appala Pentakota
IPC: H03M1/10
CPC classification number: H03M1/1019
Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.
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公开(公告)号：US20220224349A1
公开(公告)日：2022-07-14
申请号：US17568972
申请日：2022-01-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Himanshu Varshney , Viswanathan Nagarajan , Charls Babu , Narasimhan Rajagopal , Eeshan Miglani , Visvesvaraya A. Pentakota
IPC: H03M1/10
Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.
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公开(公告)号：US11784660B2
公开(公告)日：2023-10-10
申请号：US17589533
申请日：2022-01-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nagarajan Viswanathan , Himanshu Varshney , Vinam Arora , Charls Babu , Srinivas Kumar Naru
CPC classification number: H03M1/502 , H03M1/1009 , H03M1/362
Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.
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公开(公告)号：US20220247420A1
公开(公告)日：2022-08-04
申请号：US17467561
申请日：2021-09-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Narasimhan Rajagopal , Eeshan Miglani , Chirag Chandrahas Shetty , Neeraj Shrivastava , Shagun Dusad , Srinivas Kumar Reddy Naru , Nithin Gopinath , Charls Babu , Shivam Srivastava , Viswanathan Nagarajan , Jagannathan Venkataraman , Harshit Moondra , Prasanth K , Visvesvaraya Appala Pentakota
IPC: H03M1/10
Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.
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