公开(公告)号：US20170271269A1

公开(公告)日：2017-09-21

申请号：US15615963

申请日：2017-06-07

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Kezhakkedath R. Udayakumar ,  Eric H. Warninghoff ,  Alan G. Merriam ,  Rick A. Faust

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/53238 ,  H01L21/31111 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76861 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223

Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

公开(公告)号：US08778700B2

公开(公告)日：2014-07-15

申请号：US13770781

申请日：2013-02-19

Applicant: Texas Instruments Incorporated

Inventor： Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

IPC: H01L21/00 ,  H01L21/82 ,  H01L21/4763 ,  H01L21/768 ,  H01L49/02 ,  H01L27/115

CPC classification number: H01L21/76843 ,  H01L27/11509 ,  H01L28/57

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

Abstract translation: 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。

公开(公告)号：US08723241B2

公开(公告)日：2014-05-13

申请号：US13946144

申请日：2013-07-19

Applicant: Texas Instruments Incorporated

Inventor： Kezhakkedath R. Udayakumar ,  Marie Denison ,  Theodore S. Moise

IPC: H01L41/04 ,  H01L27/20 ,  H01L41/08

CPC classification number: H01L41/08 ,  H01L27/20 ,  H01L41/0533 ,  H01L41/1134 ,  H01L41/1136 ,  H01L41/1138 ,  H01L41/22 ,  H01L41/318 ,  H01L2224/18

Abstract: A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.

Abstract translation: 平面集成MEMS器件在连接到校准块的柔性元件上的介电隔离层上具有压电元件。 压电元件包含在隔离电介质上形成的具有钙钛矿结构的铁电元件。 在铁电元件上形成至少两个电极。 在压电元件上形成上部氢屏障。 在延伸到半导体衬底中的MEMS器件的周边形成有正面侧划分沟槽。 DRIE工艺从衬底的底侧去除材料以形成柔性元件，在正面单面沟槽之下从衬底去除材料，并从衬底材料形成校验物质。 压电元件与柔性元件重叠。

公开(公告)号：US20130164933A1

公开(公告)日：2013-06-27

申请号：US13770781

申请日：2013-02-19

Applicant: Texas Instruments Incorporated

Inventor： Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L27/11509 ,  H01L28/57

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

Abstract translation: 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。

公开(公告)号：US10008450B2

公开(公告)日：2018-06-26

申请号：US15615963

申请日：2017-06-07

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Kezhakkedath R. Udayakumar ,  Eric H. Warninghoff ,  Alan G. Merriam ,  Rick A. Faust

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/31111 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76861 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L24/00 ,  H01L2224/05624

Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

公开(公告)号：US09548377B2

公开(公告)日：2017-01-17

申请号：US14273704

申请日：2014-05-09

Applicant: Texas Instruments Incorporated

Inventor： Kezhakkedath R. Udayakumar ,  Kemal Tamer San

IPC: H01L29/66 ,  H01L21/324 ,  H01L27/115 ,  H01L49/02

CPC classification number: H01L29/66477 ,  H01L21/324 ,  H01L27/11507 ,  H01L28/57 ,  H01L29/66659

Abstract: Thermal treatment of a semiconductor wafer in the fabrication of integrated circuits including MOS transistors and ferroelectric capacitors, including those using lead-zirconium-titanate (PZT) ferroelectric material, to reduce variation in the electrical characteristics of the transistors. Thermal treatment of the wafer in a nitrogen-bearing atmosphere in which hydrogen is essentially absent is performed after formation of the transistors and capacitor. An optional thermal treatment of the wafer in a hydrogen-bearing atmosphere prior to deposition of the ferroelectric treatment may be performed.

Abstract translation: 包括MOS晶体管和铁电电容器在内的集成电路的制造中的半导体晶片的热处理，包括使用钛酸铅锆（PZT）铁电材料的半导体晶片，以减少晶体管的电特性的变化。 在晶体管和电容器形成之后，在基本不存在氢的含氮气氛中对晶片进行热处理。 可以在沉积铁电处理之前，在含氢气氛中对晶片进行可选的热处理。

公开(公告)号：US10665543B2

公开(公告)日：2020-05-26

申请号：US16010642

申请日：2018-06-18

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Kezhakkedath R. Udayakumar ,  Eric H. Warninghoff ,  Alan G. Merriam ,  Rick A. Faust

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

公开(公告)号：US20150079698A1

公开(公告)日：2015-03-19

申请号：US14273704

申请日：2014-05-09

Applicant: Texas Instruments Incorporated

Inventor： Kezhakkedath R. Udayakumar ,  Kemal Tamer San

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/324

CPC classification number: H01L29/66477 ,  H01L21/324 ,  H01L27/11507 ,  H01L28/57 ,  H01L29/66659

Abstract: Thermal treatment of a semiconductor wafer in the fabrication of integrated circuits including MOS transistors and ferroelectric capacitors, including those using lead-zirconium-titanate (PZT) ferroelectric material, to reduce variation in the electrical characteristics of the transistors. Thermal treatment of the wafer in a nitrogen-bearing atmosphere in which hydrogen is essentially absent is performed after formation of the transistors and capacitor. An optional thermal treatment of the wafer in a hydrogen-bearing atmosphere prior to deposition of the ferroelectric treatment may be performed.

Abstract translation: 包括MOS晶体管和铁电电容器在内的集成电路的制造中的半导体晶片的热处理，包括使用钛酸铅锆（PZT）铁电材料的半导体晶片，以减少晶体管的电特性的变化。 在晶体管和电容器形成之后，在基本不存在氢的含氮气氛中对晶片进行热处理。 可以在沉积铁电处理之前，在含氢气氛中对晶片进行可选的热处理。

公开(公告)号：US20180308802A1

公开(公告)日：2018-10-25

申请号：US16010642

申请日：2018-06-18

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Kezhakkedath R. Udayakumar ,  Eric H. Warninghoff ,  Alan G. Merriam ,  Rick A. Faust

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311

Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

公开(公告)号：US09704804B1

公开(公告)日：2017-07-11

申请号：US14974012

申请日：2015-12-18

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Kezhakkedath R. Udayakumar ,  Eric H. Warninghoff ,  Alan G. Merriam ,  Rick A. Faust

IPC: H01L21/44 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L23/53238 ,  H01L21/31111 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76861 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223

Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.