公开(公告)号：US20240071837A1

公开(公告)日：2024-02-29

申请号：US17897688

申请日：2022-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bin Liu ,  Lin Lin ,  Yu Chen Li ,  Si Si Xie ,  Zhi Yun Liu ,  Bo Jiang

IPC: H01L21/66

CPC classification number: H01L22/10 ,  H01L22/20

Abstract: A wafer metrology system having a continuous dynamic sampling scheme configured to optimize a sampling rate for AVI of process wafers in an IC fabrication flow based on acceptable quality levels. For a stable process, the process wafers may be sampled at a lower rate without negatively affecting quality control.

公开(公告)号：US09030023B2

公开(公告)日：2015-05-12

申请号：US14334738

申请日：2014-07-18

Applicant: Texas Instruments Incorporated

Inventor： Jing Wang ,  Lin Lin ,  Qiuling Jia ,  Qi Yang ,  Jianxin Liu

IPC: H01L23/00 ,  H01L23/522 ,  H01L29/78 ,  H01L23/495

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/522 ,  H01L24/03 ,  H01L24/73 ,  H01L29/7802 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/04042 ,  H01L2224/05026 ,  H01L2224/05155 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2224/05144

Abstract: A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole therethrough over a bond pad. An outer edge of the bottom dielectric layer within the contact hole extends beyond an outer edge of the top dielectric layer to define a bond pad edge. A second metal layer on a first metal layer is deposited. A first photoresist layer is formed exclusively within the contact hole. The second metal layer is wet etched to recess the second metal layer from sidewalls of the bottom dielectric layer in the contact hole. A second photoresist layer is formed exclusively within the contact hole. The first metal layer is wet etched to recess the first metal layer from the top dielectric layer. The first metal layer extends over the bond pad edge onto the bottom dielectric layer.

Abstract translation: 一种用于在半导体管芯上形成接合焊盘的方法包括形成包括底部和顶部电介质层的电介质层，所述电介质层具有穿过其的接触孔穿过接合焊盘。 接触孔内的底部电介质层的外边缘延伸超过顶部电介质层的外边缘以限定接合焊盘边缘。 沉积第一金属层上的第二金属层。 仅在接触孔内形成第一光致抗蚀剂层。 湿蚀刻第二金属层，以将第二金属层从接触孔中的底部电介质层的侧壁凹陷。 仅在接触孔内形成第二光致抗蚀剂层。 第一金属层被湿蚀刻以从顶部介电层凹入第一金属层。 第一金属层在接合焊盘边缘上延伸到底部介电层上。

公开(公告)号：US08815730B1

公开(公告)日：2014-08-26

申请号：US13934956

申请日：2013-07-03

Applicant: Texas Instruments Incorporated

Inventor： Jing Wang ,  Lin Lin ,  Qiuling Jia ,  Qi Yang ,  Jianxin Liu

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/522 ,  H01L24/03 ,  H01L24/73 ,  H01L29/7802 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/04042 ,  H01L2224/05026 ,  H01L2224/05155 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2224/05144

Abstract: A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole therethrough over a bond pad. An outer edge of the bottom dielectric layer within the contact hole extends beyond an outer edge of the top dielectric layer to define a bond pad edge. A second metal layer on a first metal layer is deposited. A first photoresist layer is formed exclusively within the contact hole. The second metal layer is wet etched to recess the second metal layer from sidewalls of the bottom dielectric layer in the contact hole. A second photoresist layer is formed exclusively within the contact hole. The first metal layer is wet etched to recess the first metal layer from the top dielectric layer. The first metal layer extends over the bond pad edge onto the bottom dielectric layer.

Abstract translation: 一种用于在半导体管芯上形成接合焊盘的方法包括形成包括底部和顶部电介质层的电介质层，所述电介质层具有穿过其的接触孔穿过接合焊盘。 接触孔内的底部电介质层的外边缘延伸超过顶部电介质层的外边缘以限定接合焊盘边缘。 沉积第一金属层上的第二金属层。 仅在接触孔内形成第一光致抗蚀剂层。 湿蚀刻第二金属层，以将第二金属层从接触孔中的底部电介质层的侧壁凹陷。 仅在接触孔内形成第二光致抗蚀剂层。 第一金属层被湿蚀刻以从顶部介电层凹入第一金属层。 第一金属层在接合焊盘边缘上延伸到底部介电层上。