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公开(公告)号：US20240319260A1
公开(公告)日：2024-09-26
申请号：US18478825
申请日：2023-09-29
Applicant: Texas Instruments Incorporated
Inventor： Tanmay Neema , Rajavelu Thinakaran , Gautam Salil Nandi , Vishal Monteiro , Deepak Kumar Meher
IPC: G01R31/28
CPC classification number: G01R31/2834 , G01R31/2889
Abstract: In described examples, a test control circuit includes a subsystem and a transition control circuit. The subsystem outputs test signals to, and receives and measures response signals of, a device under test (DUT). The transition control circuit operates the test control circuit in response to a first operational state information indicating a first mode and a first set of configuration settings; receives a Transition Trigger signal and a second operational state information indicating a second mode and a second set of configuration settings; and, by performing allowed mode changes and in response to receiving the Transition Trigger signal, transitions the test control circuit to operating in response to the second operational state information. Allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode.
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公开(公告)号：US10972092B2
公开(公告)日：2021-04-06
申请号：US16880541
申请日：2020-05-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rishubh Khurana , Tanmay Neema , Kanak Chandra Das , Atul Kumar Agrawal
Abstract: An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.
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公开(公告)号：US10673450B1
公开(公告)日：2020-06-02
申请号：US16197132
申请日：2018-11-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Atul Kumar Agrawal , Gautam Salil Nandi , Siddharth Malhotra , Tanmay Neema
Abstract: An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.
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公开(公告)号：US11936395B2
公开(公告)日：2024-03-19
申请号：US17586179
申请日：2022-01-27
Applicant: Texas Instruments Incorporated
Inventor： Tanmay Neema , Gautam Salil Nandi , Rishubh Khurana , Atul Kumar Agrawal , Deepak Kumar Meher
CPC classification number: H03M1/0604 , H03M1/1057 , H03M1/687 , H03M1/785 , H03M1/808 , H03M1/66
Abstract: In described examples, a digital-to-analog converter (DAC) includes an output, a ground, a reference voltage terminal, an input code terminal, multiple switches, multiple resistors, and a controller. The switches couple to the reference voltage terminal when activated and to the ground when deactivated. The resistors are variously coupled between corresponding ones of the switches and the output, so that activating the switches causes the DAC to output an output voltage. The controller is coupled to the input code terminal and coupled to control the switches. The controller generates an output code based on an input code in response to at least one differential nonlinearity error greater than one least significant bit voltage. The input code corresponds to a first ideal output voltage, the output code corresponds to a second, different ideal output voltage. The controller generates an output voltage by controlling the switches using the output code.
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Patent Agency Ranking
公开(公告)号：US10862493B2
公开(公告)日：2020-12-08
申请号：US16854077
申请日：2020-04-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Atul Kumar Agrawal , Gautam Salil Nandi , Siddharth Malhotra , Tanmay Neema
Abstract: An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.
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公开(公告)号：US20240337686A1
公开(公告)日：2024-10-10
申请号：US18478038
申请日：2023-09-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Tanmay Neema , Kanak Das , Rajavelu Thinakaran , Gautam Nandi
CPC classification number: G01R31/2879 , G01R31/2889 , H03F3/45475 , H03M1/662 , H03F2200/261
Abstract: The techniques and circuits, described herein, include solutions for error compensation in source measurement units (SMUs). An example SMU is capable of both sourcing current to a device under test (DUT) and measuring current through the DUT. An SMU may include a sensing resistor coupled in series with the DUT. A voltage across the sensing resistor may be measured by a current sensing amplifier in order to determine the output current through the DUT. In practice, the resistance of the sensing resistor may vary depending on manufacturing tolerances, etc. A gain of the current sensing amplifier may be calibrated in order to compensate for sensing resistor variance, which increases the accuracy with which current to the DUT can be sourced and measured.
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公开(公告)号：US12028085B2
公开(公告)日：2024-07-02
申请号：US17586155
申请日：2022-01-27
Applicant: Texas Instruments Incorporated
Inventor： Tanmay Neema , Gautam Salil Nandi , Rishubh Khurana , Atul Kumar Agrawal , Deepak Kumar Meher
CPC classification number: H03M1/0604 , H03M1/1057 , H03M1/687 , H03M1/785 , H03M1/808 , H03M1/66
Abstract: In described examples, a digital-to-analog converter includes an output, multiple most significant bit (MSB) connector resistors each having a resistance R−ΔR, multiple least significant bit (LSB) connector resistors each having a resistance R, and multiple binary arm resistors each having a resistance 2R. The MSB connector resistors are coupled in a series beginning with the output and ending with a first one of the LSB connector resistors, and the LSB connector resistors are coupled in a series beginning with the first LSB connector resistor. A terminal of one of the binary arm resistors is coupled to an ending of the LSB connector resistor series, and a terminal of each of different remaining ones of the binary arm resistors is coupled between a different pair of the MSB and/or LSB connector resistors.
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公开(公告)号：US20230238973A1
公开(公告)日：2023-07-27
申请号：US17586179
申请日：2022-01-27
Applicant: Texas Instruments Incorporated
Inventor： Tanmay Neema , Gautam Salil Nandi , Rishubh Khurana , Atul Kumar Agrawal , Deepak Kumar Meher
IPC: H03M1/06
CPC classification number: H03M1/0604
Abstract: In described examples, a digital-to-analog converter (DAC) includes an output, a ground, a reference voltage terminal, an input code terminal, multiple switches, multiple resistors, and a controller. The switches couple to the reference voltage terminal when activated and to the ground when deactivated. The resistors are variously coupled between corresponding ones of the switches and the output, so that activating the switches causes the DAC to output an output voltage. The controller is coupled to the input code terminal and coupled to control the switches. The controller generates an output code based on an input code in response to at least one differential nonlinearity error greater than one least significant bit voltage. The input code corresponds to a first ideal output voltage, the output code corresponds to a second, different ideal output voltage. The controller generates an output voltage by controlling the switches using the output code.
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公开(公告)号：US20230238972A1
公开(公告)日：2023-07-27
申请号：US17586155
申请日：2022-01-27
Applicant: Texas Instruments Incorporated
Inventor： Tanmay Neema , Gautam Salil Nandi , Rishubh Khurana , Atul Kumar Agrawal , Deepak Kumar Meher
IPC: H03M1/06
CPC classification number: H03M1/0604
Abstract: In described examples, a digital-to-analog converter includes an output, multiple most significant bit (MSB) connector resistors each having a resistance R−ΔR, multiple least significant bit (LSB) connector resistors each having a resistance R, and multiple binary arm resistors each having a resistance 2R. The MSB connector resistors are coupled in a series beginning with the output and ending with a first one of the LSB connector resistors, and the LSB connector resistors are coupled in a series beginning with the first LSB connector resistor. A terminal of one of the binary arm resistors is coupled to an ending of the LSB connector resistor series, and a terminal of each of different remaining ones of the binary arm resistors is coupled between a different pair of the MSB and/or LSB connector resistors.
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