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公开(公告)号：US10181788B2
公开(公告)日：2019-01-15
申请号：US15011242
申请日：2016-01-29
Applicant: The Regents of the University of Michigan
Inventor： Wanyeong Jung , Dennis Michael Chen Sylvester , David Theodore Blaauw
Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first voltage source providing a first voltage having a first polarity. The integrated circuit may include a second voltage source providing a second voltage having a second polarity that is opposite the first polarity. The integrated circuit may include a first circuit portion configured to receive the first and second voltages and provide one or more feedback voltages. The integrated circuit may include a second circuit portion configured to receive the first and second voltages along with the one or more feedback voltages and provide an output voltage that is proportional to the first voltage based on a rational conversion ratio that is derived by selection of at least one of the first and second voltages and the one or more feedback voltages.
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公开(公告)号：US20180365021A1
公开(公告)日：2018-12-20
申请号：US15626335
申请日：2017-06-19
Applicant: The Regents of the University of Michigan
Inventor： Yajing Chen , Trevor Mudge , Ronald Dreslinski, JR. , Shengshuo Lu , Hun Seok Kim , David Theodore Blaauw , Fu Cheng
CPC classification number: G06F9/3897 , G06F7/57 , G06F7/724 , G06F7/725 , G06F7/727 , G06F15/7867 , H04L9/0631
Abstract: Subject matter disclosed herein may relate to arithmetic units of processors, and may relate more particularly to configurable arithmetic units. Configurable arithmetic units may comprise a plurality of basic units, and may further comprise a programmable fabric to selectively connect the plurality of basic units at least in part to process one or more sets of parameters in accordance with one or more specified arithmetic operations.
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3.发明授权公开(公告)号：US09638752B2
公开(公告)日：2017-05-02
申请号：US14175015
申请日：2014-02-07
Applicant: ARM LIMITED , THE REGENTS OF THE UNIVERSITY OF MICHIGAN
Inventor： Yejoong Kim , Dennis Michael Sylvester , David Theodore Blaauw , Brian Tracy Cline
IPC: G06F19/00 , G01R31/317 , H03K3/03
CPC classification number: G01R31/31725 , H03K3/0315
Abstract: A measurement circuit and method are provided for measuring a clock node to output node delay of a flip-flop. A main ring oscillator has a plurality of main unit cells arranged in a ring, with each main unit cell comprising a flip-flop and pulse generation circuitry connected to the output node of the flip-flop. The flip-flop is responsive to receipt of an input clock pulse at the clock node to output a data value transition from the output node, and the pulse generation circuitry then generates from the data value transition an input clock pulse for a next main unit cell in the main ring, whereby the main ring oscillator generates a first output signal having a first oscillation period. A reference ring oscillator has a plurality of reference unit cells arranged to form a reference ring, and generates a second output signal having a second oscillation period, each reference unit cell comprising components configured such that the second oscillation period provides an indication of a propagation delay through the pulse generation circuitry of the main unit cells of the main ring during the first oscillation period. Calculation circuitry then determines the clock node to output node delay of the flip-flop from the first oscillation period and the second oscillation period. This provides a particularly simple and accurate mechanism for calculating the clock node to output node delay of a flip-flop.
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公开(公告)号：US09635147B2
公开(公告)日：2017-04-25
申请号：US14326684
申请日：2014-07-09
Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
Inventor： Mohammad Hassan Ghaed , Skylar Skrzyniarz , David Theodore Blaauw , Dennis Michael Sylvester
CPC classification number: H04L69/22 , H04W4/80 , H04W52/0209 , Y02D70/166
Abstract: A protocol for transmitting data from an external device to an electronic device is provided in which the external device transmits a data stream which includes the same data packet repeated multiple times. The data packet has a predetermined length and has a header portion at a predetermined position. A receiver at the electronic device captures a block of data having the predetermined length from the transmitted data stream, and a decoder rotates the captured block of data to place the header portion at the predetermined position within the data packet. This eliminates the need for an accurate jitter-free clock reference at the electronic device. By shifting power consumption and system complexity to the external unit where power is typically not constrained, the energy efficiency of the electronic device can be increased.
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5.发明授权公开(公告)号：US09396795B1
公开(公告)日：2016-07-19
申请号：US14586076
申请日：2014-12-30
Applicant: The Regents of the University of Michigan
Inventor： Supreet Jeloka , David Theodore Blaauw
IPC: G11C15/04 , G11C11/419
CPC classification number: G11C15/043 , G06F17/30982 , G11C7/067 , G11C7/1006 , G11C11/419 , G11C15/04
Abstract: A storage device has a plurality of storage cells for storing data values. Control circuitry is provided to simultaneously couple at least two cells to at least one common signal line. Sensing circuitry is provided to sense a signal on the at least one common signal line, which indicates a result of a logical operation applied to the data values stored in each of the at least two storage cells. This allows logic operations such as AND, OR, XOR, etc. to be performed within a storage device so that it is not necessary to read out each data value independently and transfer each data value to a separate processing circuit in order to find the result of the logical operation. This helps to improve performance within a data processing apparatus having the storage device.
Abstract translation: 存储装置具有用于存储数据值的多个存储单元。 提供控制电路以同时将至少两个单元耦合到至少一个公共信号线。 提供感测电路以感测至少一个公共信号线上的信号，其指示应用于存储在至少两个存储单元中的每一个中的数据值的逻辑运算的结果。 这允许在存储设备内执行诸如AND，OR，XOR等的逻辑操作，使得不需要独立地读出每个数据值，并将每个数据值传送到单独的处理电路以便找到结果 的逻辑运算。 这有助于提高具有存储装置的数据处理装置中的性能。
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Patent Agency Ranking
公开(公告)号：US10579463B2
公开(公告)日：2020-03-03
申请号：US15261712
申请日：2016-09-09
Applicant: ARM Limited , The Regents of the University of Michigan
Inventor： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , David Bull
Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.
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公开(公告)号：US10326449B2
公开(公告)日：2019-06-18
申请号：US15727382
申请日：2017-10-06
Applicant: The Regents of the University of Michigan
Inventor： Jeongsup Lee , Mehdi Saligane , David Theodore Blaauw , Dennis Michael Chen Sylvester
IPC: H03K19/0175 , H03K19/0185
Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include clock circuitry having a first plurality of logic components arranged to receive a low voltage supply, a data input signal and a clock input signal and to provide a first plurality of intermediate signals and multiple intermediate clock signals. The integrated circuit may include level converter core circuitry having voltage biasing circuitry and voltage control circuitry arranged to receive a high voltage supply, the first plurality of intermediate signals and the multiple intermediate clock signals and to provide a second plurality of intermediate signals. The integrated circuit may include latch circuitry having a second plurality of logic components arranged to receive the high voltage supply, the low voltage supply and the second plurality of intermediate signals and to provide a data output signal.
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公开(公告)号：US09966954B1
公开(公告)日：2018-05-08
申请号：US15424630
申请日：2017-02-03
Applicant: The Regents of the University of Michigan
Inventor： Kaiyuan Yang , David Theodore Blaauw , Dennis Michael Chen Sylvester
IPC: H04L9/32 , H03K19/003
CPC classification number: H03K19/00315 , H03K3/84 , H04L9/3271 , H04L9/3278
Abstract: Physically Unclonable Function (PUF) cells are described, suitable for CMOS technology, where each PUF cell is based upon a two-transistor amplifier design. A PUF cell includes a voltage generator followed by one or more amplifier stages. Also described is a method and apparatus for determining a dark bit mask for an array of PUF cells based on the two-transistor amplifier design.
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公开(公告)号：US20170178700A1
公开(公告)日：2017-06-22
申请号：US15451089
申请日：2017-03-06
Applicant: ARM Limited , The Regents of the University of Michigan
Inventor： Mahmood Khayatzadeh , Massimo Bruno Alioto , David Theodore Blaauw , Dennis Michael Chen Sylvester , Fakhruddin Ali Bohra
CPC classification number: G11C7/065 , G11C5/063 , G11C7/06 , G11C7/1012 , G11C7/106 , G11C7/18 , G11C8/16 , G11C11/419 , G11C29/026 , G11C29/028 , G11C2207/002 , G11C2207/005
Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.
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公开(公告)号：US09490779B2
公开(公告)日：2016-11-08
申请号：US13940864
申请日：2013-07-12
Applicant: The Regents of the University of Michigan
Inventor： Bharan Giridhar , Matthew Rudolph Fojtik , David Alan Fick , Dennis Michael Sylvester , David Theodore Blaauw
IPC: H03K19/003 , H03K3/037 , H03K5/13 , H03K5/135
CPC classification number: H03K3/0375 , H03K5/133 , H03K5/135
Abstract: Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying circuitry 8 to generate a pulse amplified signal. The pulse amplified signal is supplied to a second dynamic circuit stage 6 where it is used to control generation of a second stage state signal. The pulse amplifying circuitry 8 comprises a chain of serially connected skewed inverters 20, 22. The action of the pulse amplifying circuitry 8 is to reduce the probability of metastability in the output of the second dynamic stage 6.
Abstract translation: 同步电路2包括产生由脉冲放大电路8脉冲放大以产生脉冲放大信号的第一级状态信号的第一动态电路级4。 脉冲放大信号被提供给第二动态电路级6，其中它用于控制第二级状态信号的产生。 脉冲放大电路8包括串联连接的偏斜反相器20,22。脉冲放大电路8的作用是降低第二动态级6的输出中的亚稳态概率。
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