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1.发明授权公开(公告)号：US09928891B2
公开(公告)日：2018-03-27
申请号：US15023101
申请日：2014-09-18
Applicant: TOHOKU UNIVERSITY
Inventor： Takashi Ohsawa , Tetsuo Endoh
CPC classification number: G11C11/1673 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/1697 , G11C13/003 , G11C14/0081 , G11C2013/0071 , G11C2213/74 , G11C2213/79
Abstract: One end of a current path of a second field-effect transistor is connected to a gate of a first field-effect transistor. One end of a magnetic tunnel junction element is connected to one end of a current path of the first field-effect transistor. A first control terminal is connected to another end of the current path of the first field-effect transistor. A second control terminal is connected to another end of the magnetic tunnel junction element. A third control terminal is connected to another end of the current path of the second field-effect transistor.
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公开(公告)号：US20160225428A1
公开(公告)日：2016-08-04
申请号：US15023101
申请日：2014-09-18
Applicant: TOHOKU UNIVERSITY
Inventor： Takashi Ohsawa , Tetsuo Endoh
IPC: G11C11/16
CPC classification number: G11C11/1673 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/1697 , G11C13/003 , G11C14/0081 , G11C2013/0071 , G11C2213/74 , G11C2213/79
Abstract: One end of a current path of a second field-effect transistor is connected to a gate of a first field-effect transistor. One end of a magnetic tunnel junction element is connected to one end of a current path of the first field-effect transistor. A first control terminal is connected to another end of the current path of the first field-effect transistor. A second control terminal is connected to another end of the magnetic tunnel junction element. A third control terminal is connected to another end of the current path of the second field-effect transistor.
Abstract translation: 第二场效应晶体管的电流路径的一端连接到第一场效应晶体管的栅极。 磁性隧道结元件的一端连接到第一场效应晶体管的电流通路的一端。 第一控制端子连接到第一场效应晶体管的电流路径的另一端。 第二控制端子连接到磁性隧道结元件的另一端。 第三控制端子连接到第二场效应晶体管的电流通路的另一端。
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公开(公告)号：US20160224082A1
公开(公告)日：2016-08-04
申请号：US15023066
申请日：2014-09-18
Applicant: TOHOKU UNIVERSITY
Inventor： Takashi Ohsawa , Tetsuo Endoh
CPC classification number: G06F1/26 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1697 , G11C14/0081
Abstract: A memory cell (101) is connected to a word line (WL), a bit line (BL), and a power supply line (PL), and includes a flip-flop storing data based on a change in resistance value of a magnetic tunnel junction element, and, a power gating field-effect transistor including a drain that is one end of a current path connected to the power supply line, and which has another end connected to the flip-flop. The ON and OFF states of the power gating field-effect transistor are controlled based on a control signal applied to a control terminal of the power gating field-effect transistor.
Abstract translation: 存储单元（101）连接到字线（WL），位线（BL）和电源线（PL），并且包括触发器，其基于磁性电阻值的变化存储数据 隧道结元件，以及电源门控场效应晶体管，其包括作为连接到电源线的电流通路的一端的漏极，并且另一端连接到触发器。 电源门控场效应晶体管的导通和截止状态基于施加到电源门控场效应晶体管的控制端的控制信号来控制。
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公开(公告)号：US09740255B2
公开(公告)日：2017-08-22
申请号：US15023066
申请日：2014-09-18
Applicant: TOHOKU UNIVERSITY
Inventor： Takashi Ohsawa , Tetsuo Endoh
CPC classification number: G06F1/26 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1697 , G11C14/0081
Abstract: A memory cell (101) is connected to a word line (WL), a bit line (BL), and a power supply line (PL), and includes a flip-flop storing data based on a change in resistance value of a magnetic tunnel junction element, and, a power gating field-effect transistor including a drain that is one end of a current path connected to the power supply line, and which has another end connected to the flip-flop. The ON and OFF states of the power gating field-effect transistor are controlled based on a control signal applied to a control terminal of the power gating field-effect transistor.
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公开(公告)号：US20160372174A1
公开(公告)日：2016-12-22
申请号：US15101809
申请日：2014-12-03
Applicant: TOHOKU UNIVERSITY
Inventor： Takashi Ohsawa , Tetsuo Endoh
IPC: G11C11/16
CPC classification number: G11C11/1673 , G11C11/1655 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/1697 , G11C14/0081
Abstract: A memory circuit (100) includes a plurality of memory cells (50), an N-type MOSFET (30a) and an N-type MOSFET (30b). The drain of the N-type MOSFET (30a) is connected to one of a pair of bit lines, and the drain of the N-type MOSFET (30b) is connected to the other of the pair of bit lines. The gate of the N-type MOSFET (30a) is connected to the drain of the N-type MOSFET (30b), and the gate of the N-type MOSFET (30b) is connected to the drain of the N-type MOSFET (30a).
Abstract translation: 存储电路（100）包括多个存储单元（50），N型MOSFET（30a）和N型MOSFET（30b）。 N型MOSFET（30a）的漏极连接到一对位线之一，并且N型MOSFET（30b）的漏极连接到该对位线中的另一条位线。 N型MOSFET（30a）的栅极连接到N型MOSFET（30b）的漏极，并且N型MOSFET（30b）的栅极连接到N型MOSFET的漏极（ 30a）。
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Patent Agency Ranking
公开(公告)号：US09318170B2
公开(公告)日：2016-04-19
申请号：US14758100
申请日：2013-12-25
Applicant: TOHOKU UNIVERSITY
Inventor： Takashi Ohsawa , Tetsuo Endoh
CPC classification number: G11C7/22 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/0081 , G11C14/009
Abstract: A memory cell (1) includes a first storage circuit (2) with a write time t1 and a data retention time τ1 and a second storage circuit (3) with a write time t2 and a data retention time τ2 (t1
Abstract translation: 存储单元（1）包括具有写入时间t1和数据保持时间τ1的第一存储电路（2）和写入时间t2和数据保持时间τ2（t1
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公开(公告)号：US09633708B2
公开(公告)日：2017-04-25
申请号：US15101809
申请日：2014-12-03
Applicant: TOHOKU UNIVERSITY
Inventor： Takashi Ohsawa , Tetsuo Endoh
CPC classification number: G11C11/1673 , G11C11/1655 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/1697 , G11C14/0081
Abstract: A memory circuit (100) includes a plurality of memory cells (50), an N-type MOSFET (30a) and an N-type MOSFET (30b). The drain of the N-type MOSFET (30a) is connected to one of a pair of bit lines, and the drain of the N-type MOSFET (30b) is connected to the other of the pair of bit lines. The gate of the N-type MOSFET (30a) is connected to the drain of the N-type MOSFET (30b), and the gate of the N-type MOSFET (30b) is connected to the drain of the N-type MOSFET (30a).
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公开(公告)号：US09466363B2
公开(公告)日：2016-10-11
申请号：US14369974
申请日：2012-12-04
Applicant: TOHOKU UNIVERSITY
Inventor： Tetsuo Endoh , Takashi Ohsawa , Hiroki Koike , Takahiro Hanyu , Hideo Ohno
IPC: G11C14/00 , G11C13/00 , G11C11/16 , G11C15/04 , G11C19/02 , H03K3/356 , H03K3/59 , H03K19/18 , G11C29/50
CPC classification number: G11C13/0038 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0081 , G11C15/046 , G11C19/02 , G11C29/50012 , H03K3/356139 , H03K3/59 , H03K19/18
Abstract: An integrated circuit that does not involve increase in power consumption or decrease in switching probability during a write operation that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit 1 includes: a memory element 1B where write occurs when a specified period τ has elapsed after a write signal is input; and a basic circuit element 1A, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency f1 in a first operation mode in the process of memory access of the basic circuit element 1A satisfies the following relation: τ>λ1/f1(0
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公开(公告)号：US20150332745A1
公开(公告)日：2015-11-19
申请号：US14758100
申请日：2013-12-25
Applicant: TOHOKU UNIVERSITY
Inventor： Takashi Ohsawa , Tetsuo Endoh
CPC classification number: G11C7/22 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/0081 , G11C14/009
Abstract: A memory cell (1) includes a first storage circuit (2) with a write time t1 and a data retention time τ1 and a second storage circuit (3) with a write time t2 and a data retention time τ2 (t1
Abstract translation: 存储单元（1）包括具有写入时间t1和数据保持时间τ1的第一存储电路（2）和写入时间t2和数据保持时间τ2（t1
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公开(公告)号：US20140355330A1
公开(公告)日：2014-12-04
申请号：US14369974
申请日：2012-12-04
Applicant: TOHOKU UNIVERSITY
Inventor： Tetsuo Endoh , Takashi Ohsawa , Hiroki Koike , Takahiro Hanyu , Hideo Ohno
IPC: G11C13/00
CPC classification number: G11C13/0038 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0081 , G11C15/046 , G11C19/02 , G11C29/50012 , H03K3/356139 , H03K3/59 , H03K19/18
Abstract: An integrated circuit that does not involve increase in power consumption or decrease in switching probability that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit 1 includes: a memory element 1B where write occurs when a specified period τ has elapsed after a write signal is input; and a basic circuit element 1A, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency f1 in a first operation mode in the process of information processing of the basic circuit element 1A satisfies the following relation: τ>λ1/f1(0
Abstract translation: 提供了当使用现有技术的STT-MTJ装置等的锁存电路以高速运行时，不涉及增加功耗或降低切换概率的集成电路。 集成电路1包括：存储元件1B，其中在写入信号被输入之后经过了指定的周期τ时发生写入; 以及作为构成电路并具有数据保持功能的基本装置的基本电路元件1A，其特征在于，在基本电路元件1A的信息处理的处理中的第一动作模式中的动作频率f1满足以下 关系：τ>λ1/ f1（0 <λ1＆nlE; 1）。
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