公开(公告)号：US20230028652A1

公开(公告)日：2023-01-26

申请号：US17860546

申请日：2022-07-08

申请人： TOHOKU UNIVERSITY

发明人： Yoshiaki SAITO ,  Tetsuo ENDOH ,  Shoji IKEDA

IPC分类号： G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  H01L43/04 ,  H01F10/32 ,  G11C11/18 ,  G06N3/063

摘要： A magnetic multilayer film for a magnetic memory element includes an amorphous heavy metal layer having a multilayer structure in which a plurality of first layers containing Hf alternate repeatedly with a plurality of second layers containing a heavy metal excluding Hf; and a recording layer that includes a ferromagnetic layer and that is adjacent to the heavy metal layer, the ferromagnetic layer having a variable magnetization direction.

公开(公告)号：US20220406366A1

公开(公告)日：2022-12-22

申请号：US17653033

申请日：2022-03-01

申请人： TOHOKU UNIVERSITY

发明人： Hiroki KOIKE ,  Tetsuo ENDOH

IPC分类号： G11C11/4099 ,  G11C11/4091 ,  G11C11/4093

摘要： A storage circuit includes a memory cell array of memory cells each including a variable resistance type element, a resistance-voltage conversion circuit RTj to convert a resistance value of a memory cell MCij to be read to a data voltage, a reference circuit and RTR to generate a reference voltage, a sense amplifier to determine read data by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other, and an analog buffer circuit arranged between the resistance-voltage conversion circuit RTj and a first input terminal of the sense amplifier or between the reference circuit and RTR and a second input terminal of the sense amplifier. Current driving capability of the analog buffer circuit is large.

公开(公告)号：US20220093396A1

公开(公告)日：2022-03-24

申请号：US17488883

申请日：2021-09-29

申请人： GLOBALWAFERS JAPAN CO., LTD. ,  TOHOKU UNIVERSITY

发明人： Kazutaka KAMIJO ,  Etsuo FUKUDA ,  Takashi ISHIKAWA ,  Koji IZUNOME ,  Moriya MIYASHITA ,  Takao SAKAMOTO ,  Tetsuo ENDOH

IPC分类号： H01L21/02

摘要： A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.

公开(公告)号：US20210399208A1

公开(公告)日：2021-12-23

申请号：US17271200

申请日：2019-08-30

申请人： TOHOKU UNIVERSITY

发明人： Koichi NISHIOKA ,  Tetsuo ENDOH ,  Shoji IKEDA ,  Hideo SATO ,  Hiroaki HONJO

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

摘要： For implementation of a magnetoresistance effect element having a quadruple interface, a magnetoresistance effect element having a small resistance area product RA, a high magnetoresistance ratio, and a high effective magnetic anisotropy energy density Kefft* is provided.
A magnetoresistance effect element includes a first reference layer (B1), a first junction layer (11), a first divided recording layer (2), a second junction layer (12), a second divided recording layer (3), and a third junction layer (13). The first divided recording layer (2) has a configuration having a high magnetoresistance ratio (MR ratio), and the second divided recording layer (3) has a configuration having a high effective magnetic anisotropy energy density (Kefft).

公开(公告)号：US20150194437A1

公开(公告)日：2015-07-09

申请号：US14662194

申请日：2015-03-18

申请人： SK hynix Inc. ,  Tohoku University

发明人： Moon-Sik SEO ,  Tetsuo ENDOH

IPC分类号： H01L27/115 ,  H01L29/66

CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

摘要： A semiconductor device includes a channel layer protruding from a substrate and having protrusions extending from a sidewall thereof. Floating gates surrounding the channel layer are provided between the protrusions. Control gates surrounding the floating gates are stacked along the channel layer. Interlayer insulating layers are interposed between the control gates stacked along the channel layer. A level difference exists between a lateral surface of each of the floating gates, and a lateral surface of each of the protrusions.

摘要翻译： 半导体器件包括从衬底突出并具有从其侧壁延伸的突起的沟道层。 围绕通道层的浮栅设置在突起之间。 沿着沟道层堆叠围绕浮动栅极的控制栅极。 层间绝缘层介于沿通道层堆叠的控制栅之间。 每个浮动栅极的侧表面和每个突起的侧表面之间存在水平差。

公开(公告)号：US20230147268A1

公开(公告)日：2023-05-11

申请号：US17899868

申请日：2022-08-31

申请人： TOHOKU UNIVERSITY

发明人： Tetsuo ENDOH ,  Hiroshi NAGANUMA

IPC分类号： H10N52/80 ,  H10B61/00 ,  H10N52/85

CPC分类号： H10N52/80 ,  H10B61/00 ,  H10N52/85

摘要： A magnetoresistive effect element includes a reference layer, a barrier layer, a recording layer, and a channel layer that are disposed on top of one another, and a first terminal connected to the reference layer, and a second terminal and a third terminal connected to the channel layer. The channel layer includes a first channel layer and a second channel layer, the first channel layer has electrical resistance larger than electrical resistance of the second channel layer, the second terminal is connected to the first channel layer, and the third terminal is connected to the second channel layer, a write current flows between the second terminal and the third terminal via the first channel layer and the second channel layer, and a read current flows between the first terminal and the third terminal.

公开(公告)号：US20220172761A1

公开(公告)日：2022-06-02

申请号：US17395210

申请日：2021-08-05

申请人： TOHOKU UNIVERSITY

发明人： Tetsuo ENDOH ,  Hiroki KOIKE

IPC分类号： G11C11/16 ,  G11C29/04

摘要： A storage circuit includes: the array of a memory cell MC including a variable-resistance element; a conversion circuit that converts the resistance value of each memory cell into the signal level of an electric signal; a reference signal generation circuit that generates a reference signal common to a plurality of columns; a correction circuit that corrects one of the signal level of the reference signal and the signal level of the electric signal for each column of the array of the memory cell; and an RW circuit that determines data stored in the memory cell belonging to a corresponding column by comparing one of the reference level and the signal level of the electric signal, corrected by the correction circuit, and the other of the reference level and the signal level of the electric signal.

公开(公告)号：US20190304526A1

公开(公告)日：2019-10-03

申请号：US16308166

申请日：2017-05-19

申请人： TOHOKU UNIVERSITY

发明人： Hiroaki HONJO ,  Shoji IKEDA ,  Hideo SATO ,  Tetsuo ENDOH ,  Hideo OHNO

IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/10

摘要： A magnetic tunnel junction element with a high MR ratio, and can prevent a recording layer from being damaged, and magnetic memory. A reference layer includes a ferromagnetic body, and has magnetization direction fixed in the vertical direction. A barrier layer includes non-magnetic body, and disposed on one surface side of the reference layer. A recording layer is disposed to sandwich barrier layer between itself and reference layer. The recording layer includes a first ferromagnetic layer including at least one of Co and Fe, and having a magnetization direction variable in vertical direction; a first non-magnetic layer including at least one of Mg, MgO, C, Li, Al, and Si, second non-magnetic layer including at least one of Ta, Hf, W, Mo, Nb, Zr, Y, Sc, Ti, V, and Cr, and second ferromagnetic layer including at least one of Co and Fe, and having a magnetization direction variable in vertical direction.

公开(公告)号：US20190243929A1

公开(公告)日：2019-08-08

申请号：US16323146

申请日：2017-08-03

申请人： TOHOKU UNIVERSITY

发明人： Masanori NATSUI ,  Akira TAMAKOSHI ,  Takahiro HANYU ,  Akira MOCHIZUKI ,  Tetsuo ENDOH ,  Hiroki KOIKE ,  Hideo OHNO

IPC分类号： G06F17/50

摘要： A circuit design support system, a circuit design support method, a circuit design support program, and a recording medium having the program recorded thereon are provided by which a design can be performed in consideration of the stochastic operation of the stochastic operation element and the influence caused by the stochastic operation of the stochastic operation element on the operation reliability of the circuit can be evaluated.

公开(公告)号：US20180301621A1

公开(公告)日：2018-10-18

申请号：US16013093

申请日：2018-06-20

申请人： TOHOKU UNIVERSITY

发明人： Soshi SATO ,  Masaaki NIWA ,  Hiroaki HONJO ,  Shoji IKEDA ,  Hideo SATO ,  Hideo OHNO ,  Tetsuo ENDOH

IPC分类号： H01L43/10 ,  H01F10/32

CPC分类号： H01L43/10 ,  H01F10/3254 ,  H01F10/329 ,  H01L43/02 ,  H01L43/08

摘要： A spintronics element including a ferromagnetic layer containing boron, and a diffusion stopper film covering a side face of the ferromagnetic layer partially or entirely, the side face in direct contact with diffusion stopper film, so as to prevent out-diffusion of the boron contained in the ferromagnetic layer. The diffusion stopper film contains boron at a concentration higher than a concentration of the boron in a portion of the ferromagnetic layer where the ferromagnetic layer contacts the diffusion stopper film.