公开(公告)号：US20190295622A1

公开(公告)日：2019-09-26

申请号：US16128030

申请日：2018-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akira KATAYAMA

IPC: G11C11/16

Abstract: According to one embodiment, a memory device, includes a memory cell; and a first circuit that performs a first read on the memory cell to generate a first voltage, performs a reference read on the memory cell to generate a second voltage, generates first data based on the first voltage and the second voltage, writes the first data in the memory cell on which the first read has been performed, performs a second read on the memory cell in which the first data has been written to generate a third voltage, and determines data that was stored in the memory cell when the first read was performed, based on the first voltage and the third voltage.

公开(公告)号：US20180277183A1

公开(公告)日：2018-09-27

申请号：US15702430

申请日：2017-09-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiji HOSOTANI ,  Tatsuya KISHI ,  Akira KATAYAMA

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

CPC classification number: G11C11/161 ,  G11C11/1673 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

Abstract: According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. Each of the second MTJ elements includes a first ferromagnet, a second ferromagnet, and a first nonmagnet. Respective magnetizations of respective first ferromagnets of the second MTJ elements are oriented along a first direction. Respective magnetizations of respective second ferromagnets of the second MTJ elements are oriented along a second direction. One of the second MTJ elements is coupled to another one of the second MTJ elements in series or in parallel.

公开(公告)号：US20180204615A1

公开(公告)日：2018-07-19

申请号：US15920531

申请日：2018-03-14

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akira KATAYAMA

IPC: G11C13/00 ,  G11C11/16 ,  G11C7/06 ,  G11C7/04 ,  G11C7/14 ,  G11C7/18

CPC classification number: G11C13/004 ,  G11C7/04 ,  G11C7/065 ,  G11C7/14 ,  G11C7/18 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79

Abstract: A memory device includes a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node; a first path including a memory cell to be selectively connected to the first input node and provided between the first input node and a ground node; and a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node. The input value at the second input node of the sense amplifier is changed such that a change amount of the input value between two different temperatures T2 and (T2+ΔT) in a second temperature region, at a temperature higher than in a first temperature region, of the memory cell becomes larger than the change amount of the input value between two different temperatures T1 and (T1+ΔT) in the first temperature region of the memory cell, where ΔT is an increase amount of the temperature.

公开(公告)号：US20180197592A1

公开(公告)日：2018-07-12

申请号：US15913407

申请日：2018-03-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akira KATAYAMA ,  Katsuyuki FUJITA

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1675 ,  G11C11/2253 ,  G11C11/2273 ,  G11C13/0023 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2207/002

Abstract: According to one embodiment, a memory includes a bit line connected to a memory cell; and a read circuit to execute reading of data from the memory cell. The read circuit includes a first circuit having a first input terminal and detecting an output signal from the memory cell; a first transistor to control a current supplied to the memory cell based on a first control signal; and a second transistor. One terminal of the first transistor is connected to the first input terminal, the other terminal of the first transistor is connected to one terminal of the second transistor, the other terminal of the second transistor is connected to the bit line, and the one terminal and the other terminal of the first transistor are charged before data is read from the memory cell.

公开(公告)号：US20200302986A1

公开(公告)日：2020-09-24

申请号：US16565274

申请日：2019-09-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akira KATAYAMA

IPC: G11C11/16

Abstract: According to one embodiment, a semiconductor memory device comprising: a first memory layer including a plurality of memory units electrically coupled to one another; a first memory area including a first memory unit for data writing of the memory units; a second memory area including a second memory unit for data reading of the memory units; and a controller configured to write data in the first memory unit, shift the data written in the first memory unit to the second memory unit, and read data written in the second memory unit.

公开(公告)号：US20200273513A1

公开(公告)日：2020-08-27

申请号：US16559689

申请日：2019-09-04

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akira KATAYAMA

IPC: G11C11/16

Abstract: According to one embodiment, a semiconductor memory device includes control circuit configured to first node to first voltage being based on resistance of memory cell when first data is stored, write second data after first node is charged to first voltage, charge second node to second voltage being based on resistance of memory cell when second data is stored, and determine, based on first and second voltage, whether or not first data is different from second data. Control circuit includes first element including first end coupled to first node, and second end coupled to third node between first and second node, second element including first and second end coupled to first node, and third element including first end coupled to second node and second end coupled to third node.

公开(公告)号：US20200090723A1

公开(公告)日：2020-03-19

申请号：US16286526

申请日：2019-02-26

Applicant: Toshiba Memory Corporation

Inventor： Akira KATAYAMA

IPC: G11C11/16

Abstract: A nonvolatile storage device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a memory cell between the first and second wirings, a reading circuit configured to read data from the memory cell during a first and a second reading period, a writing circuit configured to write reference data into the memory cell during a writing period between the first and second reading periods, and a determination circuit configured to compare a first voltage which is based on the data read during the first reading period with a second voltage which is based on the data read during the second reading period, to determine the value of the data read during the first reading period. A current is caused to flow in the memory cell during the first reading period, the writing period, and the second reading period.