公开(公告)号：US20200251153A1

公开(公告)日：2020-08-06

申请号：US16854394

申请日：2020-04-21

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiyoshi MATSUOKA ,  Katsuyuki FUJITA

IPC: G11C5/14 ,  G11C5/02 ,  G11C11/16 ,  G11C7/02 ,  G11C5/06 ,  G11C11/34

Abstract: A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory cells, the first bank being sandwiched between the power source pad and the second bank, first power supply lines connected to the power source pad and supplying power to the first bank and not to the second bank, and second power supply lines connected to the power source pad, passing over the first bank, and supplying power to the second bank and not to the first bank.

公开(公告)号：US20180277171A1

公开(公告)日：2018-09-27

申请号：US15909502

申请日：2018-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiyoshi MATSUOKA ,  Katsuyuki FUJITA

IPC: G11C5/14 ,  G11C11/34

CPC classification number: G11C5/14 ,  G11C5/025 ,  G11C5/063 ,  G11C7/02 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/1697 ,  G11C11/34 ,  G11C27/024 ,  G11C2207/105

Abstract: A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory cells, the first bank being sandwiched between the power source pad and the second bank, first power supply lines connected to the power source pad and supplying power to the first bank and not to the second bank, and second power supply lines connected to the power source pad, passing over the first bank, and supplying power to the second bank and not to the first bank.

公开(公告)号：US20190005998A1

公开(公告)日：2019-01-03

申请号：US16126685

申请日：2018-09-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiyoshi MATSUOKA

IPC: G11C11/16 ,  G11C13/00 ,  G11C7/10

CPC classification number: G11C11/1675 ,  G11C7/1042 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/2245 ,  G11C2207/229

Abstract: A semiconductor storage device includes a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command, a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command, and a delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period.

公开(公告)号：US20180342279A1

公开(公告)日：2018-11-29

申请号：US16053608

申请日：2018-08-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiyoshi MATSUOKA

IPC: G11C11/16 ,  G11C13/00 ,  G11C11/00

CPC classification number: G11C11/1675 ,  G11C11/00 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/1697 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054

Abstract: A semiconductor storage device includes a cell array including a plurality of memory cells; a sense amplifier reading data of the memory cell; write drivers writing data to the memory cell; a sub cell area including the cell array, the sense amplifier, and the write driver; a memory area including a plurality of sub cell areas; and a control circuit, when performing a first operation of supplying a first voltage to a selected sub cell area, supplying first write data to the sub cell area which performs the first operation, for selecting the sub cell area as a target of the first operation.

公开(公告)号：US20180075893A1

公开(公告)日：2018-03-15

申请号：US15449198

申请日：2017-03-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiyoshi MATSUOKA

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/1096 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/79 ,  G11C2213/82

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing one of first and second data, first and second lines coupled to the first memory cell, a first controller capable of simultaneously outputting first and second signals, and a first driver configured to apply a first voltage to the first line and apply a second voltage to the second line according to the first data and an asserted first signal in the first data writing, and apply a third voltage to the first line and apply a fourth voltage to the second line according to the second data and an asserted second signal in the second data writing.

公开(公告)号：US20200020379A1

公开(公告)日：2020-01-16

申请号：US16579664

申请日：2019-09-23

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiyoshi MATSUOKA

IPC: G11C11/16 ,  G11C13/00

Abstract: A semiconductor storage device includes a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command, a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command, and a delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period.

公开(公告)号：US20190088303A1

公开(公告)日：2019-03-21

申请号：US15917377

申请日：2018-03-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiyoshi MATSUOKA ,  Kosuke HATSUDA

IPC: G11C11/16

Abstract: According to one embodiment, a semiconductor memory device comprises a first memory cell including a first resistance change element; and a write circuit configured to write data to the first memory cell. The write circuit includes a first circuit including a first input terminal supplied with a first signal based on read data from the first memory cell and a second input terminal supplied with a second signal based on write data to the first memory cell; and a second circuit including a first input terminal supplied with a third signal from an output terminal of the first circuit and a second input terminal supplied with a fourth signal.

公开(公告)号：US20180342278A1

公开(公告)日：2018-11-29

申请号：US16053578

申请日：2018-08-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiyoshi MATSUOKA

IPC: G11C11/16 ,  G11C13/00 ,  G11C11/00

CPC classification number: G11C11/1675 ,  G11C11/00 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/1697 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054

Abstract: A method for controlling a semiconductor storage device includes causing a control circuit to supply first write data to a sub cell area which performs a first operation of supplying a first voltage to a selected sub cell area. The semiconductor storage device includes a cell array including a plurality of memory cells, a sense amplifier reading data of the memory cell, a write driver writing data to the memory cell, the sub cell area including the cell array, the sense amplifier, and the write driver, a memory area including a plurality of sub cell areas, and the control circuit controlling the sense amplifier and the write driver.

公开(公告)号：US20180040360A1

公开(公告)日：2018-02-08

申请号：US15787212

申请日：2017-10-18

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiyoshi MATSUOKA ,  Tadashi MIYAKAWA

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0069

Abstract: A semiconductor storage device includes a first memory area; a first selection circuit which selectively connects one of first lines to one of first bit lines of the first memory area, the first lines and the first bit lines extending in a first direction; a second memory area; a second selection circuit which selectively connects one of the first lines to one of second bit lines of the second memory area, the second bit lines extending in the first direction; and a third selection circuit which selectively connects one of the first lines to a global bit line and is arranged between the first selection circuit and the second selection circuit, and configured to select the first selection circuit and the second selection circuit. The first memory area, the first selection circuit, the third selection circuit, the second selection circuit, and the second memory area are aligned in this order in the first direction.