公开(公告)号：US10803950B2

公开(公告)日：2020-10-13

申请号：US16420446

申请日：2019-05-23

申请人： Toshiba Memory Corporation

发明人： Yasuhiro Shimura ,  Tomoki Higashi ,  Sumito Ohtsuki ,  Junichi Kijima ,  Keisuke Yonehama ,  Shinichi Oosera ,  Yuki Kanamori ,  Hidehiro Shiga ,  Koki Ueno

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/32 ,  G11C11/56 ,  G11C7/20

摘要： According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.

公开(公告)号：US20190088342A1

公开(公告)日：2019-03-21

申请号：US15916570

申请日：2018-03-09

申请人： Toshiba Memory Corporation

发明人： Yasuhiro SHIMURA ,  Shinichi Oosera ,  Junichi Kijima ,  Tomoki Higashi ,  Sumito Ohtsuki ,  Tomohiro Oda ,  Keisuke Yonehama

IPC分类号： G11C16/28 ,  G06F12/0893 ,  G11C16/34 ,  G11C16/16

摘要： According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.

公开(公告)号：US10255979B1

公开(公告)日：2019-04-09

申请号：US15916570

申请日：2018-03-09

申请人： Toshiba Memory Corporation

发明人： Yasuhiro Shimura ,  Shinichi Oosera ,  Junichi Kijima ,  Tomoki Higashi ,  Sumito Ohtsuki ,  Tomohiro Oda ,  Keisuke Yonehama

IPC分类号： G11C16/28 ,  G06F12/0893 ,  G11C16/16 ,  G11C16/34

摘要： According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.

公开(公告)号：US09768189B2

公开(公告)日：2017-09-19

申请号：US15092774

申请日：2016-04-07

申请人： Toshiba Memory Corporation

发明人： Hiroshi Shinohara ,  Atsuhiro Sato ,  Keisuke Yonehama ,  Yasuyuki Baba ,  Toshifumi Minami ,  Hiroyuki Maeda ,  Shinji Saito ,  Hideyuki Kamata

IPC分类号： H01L27/115 ,  H01L27/1158 ,  H01L23/528 ,  H01L27/11582 ,  H01L21/02 ,  H01L27/11568 ,  H01L23/522 ,  H01L27/11565

CPC分类号： H01L27/1158 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.

公开(公告)号：US10854298B2

公开(公告)日：2020-12-01

申请号：US16459495

申请日：2019-07-01

申请人： Toshiba Memory Corporation

发明人： Masanobu Shirakawa ,  Takuya Futatsuyama ,  Kenichi Abe ,  Hiroshi Nakamura ,  Keisuke Yonehama ,  Atsuhiro Sato ,  Hiroshi Shinohara ,  Yasuyuki Baba ,  Toshifumi Minami

IPC分类号： G11C16/04 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C16/34

摘要： A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US10461093B2

公开(公告)日：2019-10-29

申请号：US15894832

申请日：2018-02-12

申请人： Toshiba Memory Corporation

发明人： Toshifumi Minami ,  Atsuhiro Sato ,  Keisuke Yonehama ,  Yasuyuki Baba ,  Hiroshi Shinohara ,  Hideyuki Kamata ,  Teppei Higashitsuji

IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

公开(公告)号：US10381084B2

公开(公告)日：2019-08-13

申请号：US16056835

申请日：2018-08-07

申请人： TOSHIBA MEMORY CORPORATION

发明人： Masanobu Shirakawa ,  Takuya Futatsuyama ,  Kenichi Abe ,  Hiroshi Nakamura ,  Keisuke Yonehama ,  Atsuhiro Sato ,  Hiroshi Shinohara ,  Yasuyuki Baba ,  Toshifumi Minami

IPC分类号： G11C16/04 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C16/34

摘要： A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US10818691B2

公开(公告)日：2020-10-27

申请号：US16569951

申请日：2019-09-13

申请人： Toshiba Memory Corporation

发明人： Toshifumi Minami ,  Atsuhiro Sato ,  Keisuke Yonehama ,  Yasuyuki Baba ,  Hiroshi Shinohara ,  Hideyuki Kamata ,  Teppei Higashitsuji

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11563 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11551

摘要： A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

公开(公告)号：US20190279716A1

公开(公告)日：2019-09-12

申请号：US16420446

申请日：2019-05-23

申请人： Toshiba Memory Corporation

发明人： Yasuhiro Shimura ,  Tomoki Higashi ,  Sumito Ohtsuki ,  Junichi Kijima ,  Keisuke Yonehama ,  Shinichi Oosera ,  Yuki Kanamori ,  Hidehiro Shiga ,  Koki Ueno

IPC分类号： G11C16/08 ,  G11C16/32 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  G11C11/56

摘要： According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.

公开(公告)号：US10347338B2

公开(公告)日：2019-07-09

申请号：US15699370

申请日：2017-09-08

申请人： Toshiba Memory Corporation

发明人： Yasuhiro Shimura ,  Tomoki Higashi ,  Sumito Ohtsuki ,  Junichi Kijima ,  Keisuke Yonehama ,  Shinichi Oosera ,  Yuki Kanamori ,  Hidehiro Shiga ,  Koki Ueno

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/32 ,  G11C11/56 ,  G11C7/20

摘要： According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.