公开(公告)号：US10134749B2

公开(公告)日：2018-11-20

申请号：US15490064

申请日：2017-04-18

申请人： Toshiba Memory Corporation

发明人： Mitsuhiro Noguchi ,  Yoshitaka Kubota ,  Yasuyuki Baba

IPC分类号： H01L27/115 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11575

摘要： A semiconductor memory device comprises a memory block including conductive layers at different levels from a substrate and separated from each other by a first insulation material. A memory pillar extends through the first conductive layers. A hookup region is adjacent to the memory block and includes conductive layers stacked on the substrate at levels from the substrate that corresponds to the conductive layers in the memory block. An isolation region is between the memory block and the hookup region and includes first insulating layers of a second insulating material different than the first insulating material. Each first insulating layer is at a level from the substrate that corresponds to one of the first conductive layers and each first insulating layer is between one of the conductive layers in the memory block and one of the conductive layers in hookup region.

公开(公告)号：US10020319B2

公开(公告)日：2018-07-10

申请号：US15233885

申请日：2016-08-10

申请人： Toshiba Memory Corporation

发明人： Yasuyuki Baba

IPC分类号： H01L29/66 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/423 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor memory device includes a plurality of wiring layers formed on a substrate, one or more first pillars penetrating through the wiring layers on a memory region of the substrate and in contact with the substrate, a plurality of memory transistors being formed at portions of each of the one or more first pillars that penetrate the wiring layers, and one or more second pillars penetrating through at least one of the wiring layers on a peripheral region of the substrate and in contact with the substrate. Each of the first and second pillars includes a semiconductor portion, a first insulating layer formed around the semiconductor portion, a charge accumulation layer formed around the first insulating layer, and a second insulating layer formed around the charge accumulation layer.

公开(公告)号：US09768189B2

公开(公告)日：2017-09-19

申请号：US15092774

申请日：2016-04-07

申请人： Toshiba Memory Corporation

发明人： Hiroshi Shinohara ,  Atsuhiro Sato ,  Keisuke Yonehama ,  Yasuyuki Baba ,  Toshifumi Minami ,  Hiroyuki Maeda ,  Shinji Saito ,  Hideyuki Kamata

IPC分类号： H01L27/115 ,  H01L27/1158 ,  H01L23/528 ,  H01L27/11582 ,  H01L21/02 ,  H01L27/11568 ,  H01L23/522 ,  H01L27/11565

CPC分类号： H01L27/1158 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.

公开(公告)号：US10818691B2

公开(公告)日：2020-10-27

申请号：US16569951

申请日：2019-09-13

申请人： Toshiba Memory Corporation

发明人： Toshifumi Minami ,  Atsuhiro Sato ,  Keisuke Yonehama ,  Yasuyuki Baba ,  Hiroshi Shinohara ,  Hideyuki Kamata ,  Teppei Higashitsuji

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11563 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11551

摘要： A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

公开(公告)号：US10074434B2

公开(公告)日：2018-09-11

申请号：US15791178

申请日：2017-10-23

申请人： Toshiba Memory Corporation

发明人： Masanobu Shirakawa ,  Takuya Futatsuyama ,  Kenichi Abe ,  Hiroshi Nakamura ,  Keisuke Yonehama ,  Atsuhiro Sato ,  Hiroshi Shinohara ,  Yasuyuki Baba ,  Toshifumi Minami

IPC分类号： G11C16/04 ,  G11C16/14 ,  G11C11/56 ,  G11C29/42 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/1157 ,  G11C16/34

CPC分类号： G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3445 ,  G11C29/42 ,  H01L27/1157 ,  H01L27/11582

摘要： A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US09893078B2

公开(公告)日：2018-02-13

申请号：US14630507

申请日：2015-02-24

申请人： Toshiba Memory Corporation

发明人： Toshifumi Minami ,  Atsuhiro Sato ,  Keisuke Yonehama ,  Yasuyuki Baba ,  Hiroshi Shinohara ,  Hideyuki Kamata ,  Teppei Higashitsuji

IPC分类号： H01L29/49 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

公开(公告)号：US10854298B2

公开(公告)日：2020-12-01

申请号：US16459495

申请日：2019-07-01

申请人： Toshiba Memory Corporation

发明人： Masanobu Shirakawa ,  Takuya Futatsuyama ,  Kenichi Abe ,  Hiroshi Nakamura ,  Keisuke Yonehama ,  Atsuhiro Sato ,  Hiroshi Shinohara ,  Yasuyuki Baba ,  Toshifumi Minami

IPC分类号： G11C16/04 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C16/34

摘要： A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US10461093B2

公开(公告)日：2019-10-29

申请号：US15894832

申请日：2018-02-12

申请人： Toshiba Memory Corporation

发明人： Toshifumi Minami ,  Atsuhiro Sato ,  Keisuke Yonehama ,  Yasuyuki Baba ,  Hiroshi Shinohara ,  Hideyuki Kamata ,  Teppei Higashitsuji

IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

公开(公告)号：US10381084B2

公开(公告)日：2019-08-13

申请号：US16056835

申请日：2018-08-07

申请人： TOSHIBA MEMORY CORPORATION

发明人： Masanobu Shirakawa ,  Takuya Futatsuyama ,  Kenichi Abe ,  Hiroshi Nakamura ,  Keisuke Yonehama ,  Atsuhiro Sato ,  Hiroshi Shinohara ,  Yasuyuki Baba ,  Toshifumi Minami

IPC分类号： G11C16/04 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C16/34

摘要： A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.